View AD3500_2834170.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

AD3500/ada3500 users manual ? real time devices usa, inc. ?accessing the analog world? ? publication no. 3500-5/1/97 www.datasheet.co.kr datasheet pdf - http://www..net/
www.datasheet.co.kr datasheet pdf - http://www..net/
? AD3500/ada3500 users manual real time devices usa, inc. post office box 906 state college, pennsylvania 16804 usa phone: (814) 234-8087 fax: (814) 234-5218 www.datasheet.co.kr datasheet pdf - http://www..net/
published by real time devices usa, inc. p.o. box 906 state college, pa 16804 usa copyright ? 1997 by real time devices, inc. all rights reserved printed in u.s.a. 5/1/97 www.datasheet.co.kr datasheet pdf - http://www..net/
table of contents i introduction ................................................................................................................... ................. i -1 analog-to-digital conversion ................................................................................................... ............................. i -3 digital-to-analog conversion (ada3500) ......................................................................................... .................. i -4 8254 timer/counters ............................................................................................................ .................................. i -4 digital i/o .................................................................................................................... ........................................... i -4 what comes with your board ..................................................................................................... ......................... i -4 board accessories .............................................................................................................. ..................................... i -4 hardware accessories ........................................................................................................... ............................. i -4 using this manual .............................................................................................................. ................................... i -5 when you need help ............................................................................................................. ................................ i -5 chapter 1 board settings ................................................................................................. 1-1 factory-configured switch and jumper settings .................................................................................. ............... 1-3 p10 p3 signal select (factory setting: p3-43, ot1; p3-44, ot2) .............................................................. 1- 5 p9 user tc clock/gate source select (factory setting: see figure 1-3) ................................................... 1-5 s1 base address (factory setting: 300 hex (768 decimal)) ..................................................................... .. 1-8 s2 single-ended input with dedicated ground (factory setting: open) ................................................. 1-9 s3 differential input ground reference (factory setting: open) ............................................................ 1-9 p5, p6, p7 and p8, pull-up/pull-down resistors on digital i/o lines ............................................................ ... 1-10 chapter 2 board installation ....................................................................................... 2-1 board installation ............................................................................................................. ..................................... 2-3 external i/o connections ....................................................................................................... ............................... 2-3 connecting the analog input pins ............................................................................................... ..................... 2-4 connecting the analog outputs .................................................................................................. ...................... 2-5 connecting the timer/counters and digital i/o .................................................................................. ............ 2-5 running the 3500diag diagnostics program ....................................................................................... .............. 2-5 chapter 3 hardware description ................................................................................ 3-1 a/d conversion circuitry ....................................................................................................... .............................. 3-3 analog inputs .................................................................................................................. .................................. 3-3 channel-gain scan memory ....................................................................................................... ....................... 3-4 a/d converter .................................................................................................................. ................................. 3-4 1024 sample buffer ............................................................................................................. .............................. 3-4 data transfer .................................................................................................................. ................................... 3-4 d/a converters (ada3500) ....................................................................................................... ........................... 3-4 timer/counters ................................................................................................................. ..................................... 3-6 digital i/o .................................................................................................................... .......................................... 3-6 chapter 4 i/o mapping ....................................................................................................... .... 4-1 defining the i/o map ........................................................................................................... ................................. 4-3 ba + 0: clear/program clear register (read/write) ............................................................................. ........ 4-4 ba + 2: read status/program control register (read/write) ..................................................................... .. 4-5 ba + 4: read converted data/load channel-gain & digital data (read/write) ........................................ 4-7 ba + 6: start convert/program trigger modes (read/write) ...................................................................... . 4-9 ba + 8: load dac sample counter/program irq source & channel (read/write) ................................ 4-11 ba + 10: update dac/program dac configuration register (read/write) .............................................. 4-12 www.datasheet.co.kr datasheet pdf - http://www..net/
ii ba + 12: load a/d delay counter/d/a converter 1 data (read/write) .................................................... 4-13 ba + 14: load a/d sample counter/d/a converter 2 data (read/write) .................................................. 4-13 ba + 16: tc counter 0 (read/write) ............................................................................................. ............... 4-14 ba + 18: tc counter 1 (read/write) ............................................................................................. ............... 4-14 ba + 20: tc counter 2 (read/write) ............................................................................................. ............... 4-14 ba + 22: timer/counter control word (write only) ............................................................................... .... 4-14 ba + 24: digital i/o port 0 (port 2), bit programmable port (read/write) ................................................. 4-14 ba + 26: digital i/o port 1 (port 3), byte programmable port (read/write) .............................................. 4-15 ba + 28: read/program port 0 (port 2) direction/mask/compare registers (read/write) ........................ 4-15 ba + 30: read digital irq status/program digital mode (read/write) ..................................................... 4-16 programming the 3500 ........................................................................................................... ............................. 4-17 clearing and setting bits in a port ............................................................................................ .......................... 4-17 chapter 5 a/d conversions ................................................................................................ 5-1 before starting conversions: initializing the board ............................................................................ ................ 5-3 before starting conversions: programming channel, gain and input type ....................................................... 5-3 before starting conversions: programming the channel-gain table ................................................................ . 5-4 16-bit a/d table ............................................................................................................... ................................ 5-4 channel select, gain select and input type ..................................................................................... ............... 5-4 pause bit ...................................................................................................................... ...................................... 5-5 skip bit ....................................................................................................................... ....................................... 5-5 8-bit digital table ............................................................................................................ ................................ 5-6 setting up a/d and digital tables .............................................................................................. ..................... 5-6 using the channel-gain table for a/d conversions ............................................................................... ........ 5-7 channel-gain table and throughput rates ........................................................................................ .............. 5-7 channel-gain data store enable (ba + 2, bit 4) ................................................................................. ............. 5-7 a/d conversion modes ........................................................................................................... .............................. 5-7 types of conversions ........................................................................................................... ........................... 5-10 starting an a/d conversion ..................................................................................................... ....................... 5-12 monitoring conversion status ................................................................................................... ..................... 5-12 halting conversions ............................................................................................................ ............................ 5-12 reading the converted data ..................................................................................................... .......................... 5-13 reading data with the channel-gain data store bit disabled ..................................................................... . 5-13 reading data with the channel-gain data store bit enabled ...................................................................... . 5-14 programming the pacer clock .................................................................................................... ......................... 5-16 selecting 16-bit or 32-bit pacer clock ......................................................................................... .................. 5-16 programming steps .............................................................................................................. ........................... 5-16 programming the burst clock .................................................................................................... ......................... 5-17 programming the sample counter ................................................................................................. ..................... 5-18 using the sample counter to create large data arrays ........................................................................... .... 5-18 chapter 6 data transfers using dma ......................................................................... 6-1 choosing a dma channel ......................................................................................................... ........................... 6-3 allocating a dma buffer ........................................................................................................ .............................. 6-3 calculating the page and offset of a buffer .................................................................................... ..................... 6-4 setting the dma page register .................................................................................................. .......................... 6-5 the dma controller ............................................................................................................. ................................ 6-6 dma mask register .............................................................................................................. ............................ 6-6 dma mode register .............................................................................................................. ........................... 6-7 programming the dma controller ................................................................................................. .................. 6-7 programming the 3500 for dma ................................................................................................... ....................... 6-7 monitoring for dma done ........................................................................................................ ........................... 6-7 dual dma mode .................................................................................................................. ................................. 6-7 common dma problems ............................................................................................................ .......................... 6-8 www.datasheet.co.kr datasheet pdf - http://www..net/
iii chapter 7 interrupts ........................................................................................................ ... 7-1 software selectable interrupt sources .......................................................................................... ........................ 7-3 software selectable interrupt channel .......................................................................................... ....................... 7-4 advanced digital interrupts .................................................................................................... .............................. 7-4 event mode ..................................................................................................................... .................................. 7-4 match mode ..................................................................................................................... .................................. 7-4 sampling digital lines for change of state ..................................................................................... ................ 7-4 basic programming for interrupt handling ....................................................................................... .................. 7-5 what is an interrupt? .......................................................................................................... ............................... 7-5 interrupt request lines ........................................................................................................ ............................. 7-5 8259 programmable interrupt controller ......................................................................................... ................ 7-5 interrupt mask register (imr) .................................................................................................. ................... 7-5 end-of-interrupt (eoi) command ................................................................................................. ............... 7-6 what exactly happens when an interrupt occurs? ................................................................................. ........ 7-6 using interrupts in your programs .............................................................................................. ..................... 7-6 writing an interrupt service routine (isr) ..................................................................................... ................ 7-6 saving the startup interrupt mask register (imr) and interrupt vector ........................................................ 7- 7 restoring the startup imr and interrupt vector ................................................................................. ............. 7-8 common interrupt mistakes ...................................................................................................... ....................... 7-8 chapter 8 d/a conversions ................................................................................................ 8-1 1024 sample buffer ............................................................................................................. .............................. 8-4 dac cycle bit .................................................................................................................. ................................ 8-4 dma transfer ................................................................................................................... ................................ 8-5 dac sample counter ............................................................................................................. ........................... 8-6 chapter 9 timer/counters ................................................................................................ 9-1 chapter 10 digital i/o ...................................................................................................... ... 10-1 port 0 and port 2, bit programmable digital i/o ................................................................................ ............... 10-3 advanced digital interrupts: mask and compare registers ........................................................................ .. 10-3 port 1 and port 3, port programmable digital i/o ............................................................................... ............... 10-3 resetting the digital circuitry ................................................................................................ ............................ 10-3 strobing data into port 0 ...................................................................................................... ............................... 10-3 chapter 11 example programs ..................................................................................... 11-1 c programs ..................................................................................................................... ...................................... 11-3 quick basic programs ........................................................................................................... .............................. 11-3 chapter 12 calibration..................................................................................................... 1 2-1 required equipment ............................................................................................................. ............................... 12-3 a/d calibration ................................................................................................................ ................................... 12-5 gain adjustment ................................................................................................................ .............................. 12-6 d/a calibration ................................................................................................................ ................................... 12-6 appendix a AD3500/ada3500 specifications ................................................................. a-1 appendix b p3 & p4 connector pin assignments .................................................... b-1 appendix c component data sheets ............................................................................ c-1 appendix d warranty .......................................................................................................... . d-1 www.datasheet.co.kr datasheet pdf - http://www..net/
list of illustrations 1-1 board layout showing factory-configured settings ............................................................................ . 1-4 1-2 p3 signal select jumpers, p10 ............................................................................................... .................. 1-5 1-3 user tc clock/gate sources jumpers, p9 ...................................................................................... ........ 1-6 1-4 user tc circuit diagram ..................................................................................................... .................... 1-7 1-5 base address switch, s1 ..................................................................................................... .................... 1-8 1-6 8-position dip switch ....................................................................................................... ....................... 1-9 1-7 ports 0, 1, 2 and 3 pull-up/pull-down resistor connections ................................................................ 1- 10 2-1 p3 & p4 i/o connector pin assignments ....................................................................................... ......... 2-3 2-2 3500 input connection diagram ............................................................................................... .............. 2-4 3-1 3500 block diagram .......................................................................................................... ...................... 3-3 3-2 timer/counter circuit block diagram ......................................................................................... .......... 3-5 4-1 using the skip bit .......................................................................................................... .......................... 4-8 5-1 setting the skip bit ........................................................................................................ .......................... 5-5 5-2 timing diagram for sampling channels 1 and 4 ................................................................................ ... 5-5 5-3 a/d conversion select circuitry ............................................................................................. ................ 5-8 5-4 external trigger single cycle vs. repeat cycle .............................................................................. .... 5-10 5-5 timing diagram, single conversion ........................................................................................... .......... 5-10 5-6 timing diagram, multiple conversions ........................................................................................ ....... 5-11 5-7 timing diagram, random channel scan ......................................................................................... .... 5-11 5-8 timing diagram, programmable burst .......................................................................................... ....... 5-11 5-9 timing diagram, programmable multiscan ...................................................................................... ... 5-12 5-10 sample buffer circuitry .................................................................................................... ..................... 5-14 5-11 pacer clock block diagram .................................................................................................. ................ 5-16 5-12 timing diagram for cycling the sample counter .............................................................................. .. 5-19 7-1 digital interrupt timing diagram ............................................................................................ ............... 7-4 9-1 user tc circuit diagram ..................................................................................................... .................... 9-3 12-1 board layout ............................................................................................................... ........................... 12-4 iv www.datasheet.co.kr datasheet pdf - http://www..net/
i -1 introduction www.datasheet.co.kr datasheet pdf - http://www..net/
i -2 www.datasheet.co.kr datasheet pdf - http://www..net/
i -3 the AD3500 and ada3500 datamaster? boards turn your ibm ? pc-at or compatible computer into a high-speed, high-performance data acquisition and control system. installed within a single expansion slot in the computer, these boards feature: ? 8 differential, 8 single-ended with dedicated grounds, or 16 single-ended analog input channels, ? 16-bit, 10 microsecond analog-to-digital converter with 100 khz at throughput, ? 10 volt input range, ? programmable gains of 1, 2, 4, 8, 16, 32, 64 & 128, ? 1024 x 24 channel-gain scan memory with skip bit, ? software, pacer clock and external trigger modes, ? scan, burst and multiburst using the channel-gain table, ? 16-bit programmable high speed sample counter and 16-bit delay counter, ? a/d dma transfer, ? 1024 sample a/d buffer for gap-free high speed sampling under windows? and dos ? pre-, post- and about-trigger modes, ? 16 bit programmable digital i/o lines with advanced digital interrupt modes, ? 16 port programmable digital i/o lines, ? twelve 16-bit timer/counters (three available to user) and on-board 8 mhz clock, ? two 16-bit, 10 microsecond digital-to-analog output channels with 100 khz throughput (ada3500 only), ? 10 volt analog output range, ? d/a dma transfer, ? two 1024 sample d/a buffers for gap-free high speed output under windows? and dos ? programmable interrupt source, ? windows? example programs in visual basic and c, ? dos example programs with source code in basic and c, ? diagnostics software. the following paragraphs briefly describe the major functions of the 3500. a detailed discussion of board functions is included in subsequent chapters. analog-to-digital conversion the 3500 is software configurable on a channel-by-channel basis for up to 16 single-ended or 8 differential analog inputs. in addition, an on-board switch allows you to set any of eight inputs as single-ended with dedicated ground. overvoltage protection to 12 volts is provided at the inputs. the common mode input voltage for differential operation is 10 volts. a/d conversions are typically performed in 10 microseconds, and the maximum throughput rate of the board is 100 khz. conversions are controlled by software command, by an on-board pacer clock, by using triggers to start and stop sampling, or by using the sample counter to acquire a specified number of samples. several trigger sources can be used to turn the pacer clock on and off, giving you exceptional flexibility in data acquisition. scan, burst, and multiburst modes are supported by using the channel-gain scan memory. a first in, first out (fifo) sample buffer helps your computer manage the high throughput rate of the a/d converter by acting as an elastic storage bin for the converted data. even if the computer does not read the data as fast as conversions are per- formed, conversions can continue until the fifo is full. the converted data can be transferred to pc memory in one of three ways. direct memory access (dma) transfer supports conversion rates of up to 100,000 samples per second. data also can be transferred using the programmed i/o mode or the interrupt mode. a special interrupt mode using a rep ins (repeat input string) instruction supports very high speed data transfers. by generating an interrupt when the fifos half-full flag is set, a rep ins instruction can be executed, transferring data to pc memory and emptying the fifo buffer at the maxi- mum rate allowed by the data bus. the mode of transfer and dma channel are chosen through software. the pc data bus is used to read and/or transfer data to pc memory. in the dma transfer mode, you can make continuous transfers directly to pc memory without going through the processor. www.datasheet.co.kr datasheet pdf - http://www..net/
i -4 digital-to-analog conversion (ada3500) the digital-to-analog (d/a) circuitry features two independent 16-bit analog output channels with a range of - 10 to +10 volts. each channel has it's own 1024 sample buffer for data storage before being output. data can be continuosly written to the buffer producing a non-repetetive output waveform or a set of data can be written into the buffer and continuosly cycled to produce a repeating waveform. data can be written into the output buffers by i/o instruction or by dma transfer. updating of the analog outputs can be done through software or by several different clocks and triggers. the outputs can be updated simultaneously or independently. 8254 timer/counters four 8254 programmable interval timers provide twelve (three each) 16-bit, 8 mhz timer/counters to support a wide range of board operations and user timing and counting functions. nine of the 16-bit timer/counters are used for board operation. two are used for the pacer clock, one is used for the burst clock, one is used for the a/d sample counter, one is used for the a/d delay counter, two are used for d/a output clocks and two are used for d/ a sample counters. the three remaining timer/counters are available for user functions. digital i/o the 3500 has 32 buffered ttl/cmos digital i/o lines which are grouped in 2 digital i/o chips each with eight independent, bit programmable lines at port 0 and port 2, and an 8-bit programmable port at port 1 and port 3. the bit programmable lines support rtds two advanced digital interrupt modes. an interrupt can be gener- ated when any bit changes value (event interrupt), or when the lines match a programmed value (match interrupt). for either mode, masking can be used to monitor selected lines. bit configurable pull-up or pull-down resistors are provided for all 32 lines. instructions for activating these pull-up/pull-down resistors are given at the end of chapter 1, board settings . port 0 and port 1 are accessed through the rear p3 connector. port 2 and port 3 are accessed at the on-board p4 connector. what comes with your board you receive the following items in your board package: ? AD3500 or ada3500 das board ? windows? example programs in visual basic and c ? example programs in basic and c with source code & diagnostics software ? users manual if any item is missing or damaged, please call real time devices customer service department at (814) 234-8087. if you require service outside the u.s., contact your local distributor. board accessories in addition to the items included in your 3500 package, real time devices offers a full line of software and hardware accessories. call your local distributor or our main office for more information about these accessories and for help in choosing the best items to support your boards application. hardware accessories hardware accessories for the 3500 include the tmx32 analog input expansion board with thermocouple compensation which can expand a single input channel on your 3500 to 16 differential or 32 single-ended input channels, the op series optoisolated digital input boards, the mr series mechanical relay output boards, the or16 optoisolated digital input/mechanical relay output board, the usf8 universal sensor interface with sensor excitation, the ts16 thermocouple sensor board, the tb50 terminal board and xb50 prototype/terminal board for easy signal access and prototype development, and xd50 twisted pair wire flat ribbon cable assembly for external interfacing. www.datasheet.co.kr datasheet pdf - http://www..net/
i -5 using this manual this manual is intended to help you install your new board and get it running quickly, while also providing enough detail about the board and its functions so that you can enjoy maximum use of its features even in the most complex applications. we assume that you already have an understanding of data acquisition principles and that you can customize the example software or write your own application programs. when you need help this manual and the example programs in the software package included with your board provide enough information to properly use all of the boards features. if you have any problems installing or using this board, contact our technical support department, (814) 234-8087, during regular business hours, eastern standard time or eastern daylight time, or send a fax requesting assistance to (814) 234-5218. when sending a fax request, please include your companys name and address, your name, your telephone number, and a brief description of the problem. you can also contact us through our e-mail address techsupport@rtdusa.com . www.datasheet.co.kr datasheet pdf - http://www..net/
i -6 www.datasheet.co.kr datasheet pdf - http://www..net/
1-1 chapter 1 board settings the AD3500 and ada3500 have jumper and switch settings you can change if necessary for your application. the board is factory-configured as listed in the table and shown on the layout diagram in the beginning of this chapter. should you need to change these settings, use these easy-to-follow instructions before you install the board in your computer. also note that by setting the jumpers as desired on header connectors p5, p6, p7 and p8, you can configure each digital i/o line to be pulled up or pulled down. this procedure is explained at the end of this chapter. www.datasheet.co.kr datasheet pdf - http://www..net/
1-2 www.datasheet.co.kr datasheet pdf - http://www..net/
1-3 factory-configured switch and jumper settings table 1-1 lists the factory settings of the user-configurable jumpers and switches on the 3500. figure 1-1 shows the board layout and the locations of the factory-set jumpers. the following paragraphs explain how to change the factory settings. pay special attention to the setting of s1, the base address switch, to avoid address contention when you first use your board in your system. table 1-1 factory settings switch/ jumper function controlled factory settings (jumpers installed) p5 activates pull-up/ pull-down resistors on port 2 digital i/o lines all bits pulled up (jumpers installed between com & v) p6 activates pull-up/ pull-down resistors on port 3 digital i/o lines all bits pulled up (jumpers installed between com & v) p7 activates pull-up/ pull-down resistors on port 0 digital i/o lines all bits pulled up (jumpers installed between com & v) p8 activates pull-up/ pull-down resistors on port 1 digital i/o lines all bits pulled up (jumpers installed between com & v) p9 sets the clock and gate source for user tc counters 0, 1 & 2 counters cascaded with 8 mhz clock source and +5v gate source (see figure 1-3) p10 selects the signals available at p3, pins 43 and 44 p3-43: ot1; p3-44: ot2 s1 sets the base address 300 hex (768 decimal) s2 when closed, provides a dedicated ground for the corresponding single-ended input channel open (no ground connection) s3 when closed, provides a separate ground reference for the corresponding differential input channel through a 10k resistor open (no connection to 10k) www.datasheet.co.kr datasheet pdf - http://www..net/
1-4 fig. 1-1 board layout showing factory-configured settings www.datasheet.co.kr datasheet pdf - http://www..net/
1-5 p10 p3 signal select (factory setting: p3-43, ot1; p3-44, ot2) this header connector, shown in figure 1-2, lets you select the output signal from the board that is present at i/o connector p3, pins 43 and 44. the left four locations are used to select the signal at p3-43: the output from digital interrupt 2 (dig2), digital interrupt 1 (dig1), user tc counter 1 output (ot1) or user tc counter 0 output (ot0). the remaining two locations are used to select the signal at p3-44: the output from user tc counter 1 (ot1) or user tc counter 2 (ot2). p9 user tc clock/gate source select (factory settings: see figure 1-3) this header connector, shown in figure 1-3, lets you select the clock and gate sources for user tc counters 0, 1, and 2, the 16-bit timer/counters available for user functions. figure 1-4 shows a block diagram of the user tc circuitry to help you in making these connections. the top two groups of pins labeled clk0 and gate0 on the left side are the clock and gate sources for counter 0. the three clock sources available are: osc, the on-board 8 mhz clock; eclk, the external clock source brought on board through i/o connector p3, pin 45; and epclk, an external pacer clock brought on board through i/o connector p3, pin 41. the three gate sources are: +5v, which pulls the gate line high; egt1, an external gate brought on board through i/o connector p3, pin 42; and egt2, a second external gate brought on board through i/o connector p3, pin 46. the next two groups of pins labeled clk1 and gate1 on the left side are the clock and gate sources for counter 1. the four clock sources available are: ot0, the output of counter 0 (for cascading counters); osc, the on-board 8 mhz clock; eclk, the external clock source brought on board through i/o connector p3, pin 45; and epclk, an external pacer clock brought on board through i/o connector p3, pin 41. the three gate sources are: +5v, which pulls the gate line high; egt1, an external gate brought on board through i/o connector p3, pin 42; and egt2, a second external gate brought on board through i/o connector p3, pin 46. the bottom two groups of pins labeled clk2 and gate2 on the left side are the clock and gate sources for counter 2. the four clock sources available are: ot1, the output of counter 1 (for cascading counters); osc, the on-board 8 mhz clock; eclk, the external clock source brought on board through i/o connector p3, pin 45; and epclk, an external pacer clock brought on board through i/o connector p3, pin 41. the four gate sources are: +5v, which pulls the gate line high; egt1, an external gate brought on board through i/o connector p3, pin 42; egt2, a second external gate brought on board through i/o connector p3, pin 46; and ot1, the output of counter 1. the factory settings are shown in figure 1-3. as shown, all three counters are cascaded, the clock source for counter 0 is the on-board 8 mhz clock, and the gate source for all three counters is +5v. dig2 dig1 ot1 ot0 ot1 ot2 p10 p3-43 p3-44 fig. 1-2 p3 signal select jumpers, p10 www.datasheet.co.kr datasheet pdf - http://www..net/
1-6 osc eclk epclk +5v egt1 egt2 ot0 osc eclk epclk +5v egt1 egt2 ot1 osc eclk epclk +5v egt1 egt2 ot1 clk0 gate0 clk1 gate1 clk2 gate2 p9 fig. 1-3 user tc clock/gate sources jumpers, p9 www.datasheet.co.kr datasheet pdf - http://www..net/
1-7 fig. 1-4 user tc circuit diagram clocktcu50 counter 0 clk gate out counter 1 clk gate out counter 2 clk gate out 8mhz 16-bit pacer clock pacer clock gate control 32-bit pacer clock burst clock gate control burst clock counter1 tc u51 counter 0 clk gate out counter 1 clk gate out counter 2 clk gate out +5 v +5 v +5 v sample count clock sample count delay count clock delay count dac2 count clock dac2 count 3500 i/o connector p3 ext pclk pin 44 ext gate 1 ext clk user tc u53 counter 0 clk gate out counter 1 clk gate out counter 2 clk gate out 8mhz pin 45 pin 41 pin 42 pin 46 ext gate 2 +5 v p10 dig int 1 p9 counter2 tc u52 counter 0 clk gate out counter 1 clk gate out counter 2 clk gate out +5 v +5 v +5 v 8mhz dac1 clock 8mhz dac2 clock dac1 count clock dac1 count pin 43 dig int 2 www.datasheet.co.kr datasheet pdf - http://www..net/
1-8 s1 base address (factory setting: 300 hex (768 decimal)) one of the most common causes of failure when you are first trying your board is address contention. some of your computers i/o space is already occupied by internal i/o and other peripherals. when the 3500 attempts to use i/o address locations already used by another device, contention results and the board does not work. to avoid this problem, the 3500 has an easily accessible dip switch, s1, which lets you select any one of 16 starting addresses in the computers i/o. should the factory setting of 300 hex (768 decimal) be unsuitable for your system, you can select a different base address simply by setting the switches to any one of the values listed in table 1-2. the table shows the switch settings and their corresponding decimal and hexadecimal (in parentheses) values. make sure that you verify the order of the switch numbers on the switch (1 through 4) before setting them. when the switches are pulled forward, they are open, or set to logic 1, as labeled on the dip switch package. when you set the base address for your board, record the value in the table inside the back cover. figure 1-5 shows the dip switch set for a base address of 300 hex (768 decimal). table 1-2 base address switch settings, s1 base address decimal / (hex) switch setting 4 3 2 1 base address decimal / (hex) switch setting 4 3 2 1 512 / (200) 0 0 0 0 768 / (300) 1 0 0 0 544 / (220) 0 0 0 1 800 / (320) 1 0 0 1 576 / (240) 0 0 1 0 832 / (340) 1 0 1 0 608 / (260) 0 0 1 1 864 / (360) 1 0 1 1 640 / (280) 0 1 0 0 896 / (380) 1 1 0 0 672 / (2a0) 0 1 0 1 928 / (3a0) 1 1 0 1 704 / (2c0) 0 1 1 0 960 / (3c0) 1 1 1 0 736 / (2e0) 0 1 1 1 992 / (3e0) 1 1 1 1 0 = closed, 1 = open fig. 1-5 base address switch, s1 www.datasheet.co.kr datasheet pdf - http://www..net/
1-9 s2 single-ended input with dedicated ground (factory setting: open (no grounded inputs)) the 8-position dip switch s2 lets you connect any of eight input channels on the board as single-ended with dedicated ground. by closing the corresponding dip switch (s2-1 is channel 1, s2-2 is channel 2, and so on), the input circuit is grounded. figure 1-6 shows an 8-position dip switch. note that if you are using a dip switch on s3 to provide a separate ground reference through a 10 kilohm resistor for a differential input channel, the corresponding switch on s2 must be open (no connection to ground), or the 10k resistor will be bypassed. for a clearer understanding of the operation of s2 and s3, see the input connec- tion diagram, figure 2-2 on page 2-4. s3 differential input ground reference (factory setting: open (no ground reference)) the 8-position dip switch s3 lets you connect any differential input channel to a 10 kilohm pull-down resistor to provide a separate ground reference for signal sources that may require it. by closing the corresponding dip switch (s2-1 is channel 1, s2-2 is channel 2, and so on), the input circuit is connected through a 10k resistor. figure 1-6 shows an 8-position dip switch. note that if you are using a dip switch on s3 to provide a separate ground reference through a 10 kilohm resistor for a differential input channel, the corresponding switch on s2 must be open (no connection to ground), or the 10k resistor will be bypassed. for a clearer understanding of the operation of s2 and s3, see the input connec- tion diagram, figure 2-2 on page 2-4. fig. 1-6 8-position dip switch www.datasheet.co.kr datasheet pdf - http://www..net/
1-10 p5, p6, p7 and p8, pull-up/pull-down resistors on digital i/o lines the 3500 has 32 ttl/cmos compatible digital i/o lines which can be interfaced with external devices. these lines are divided into two groups: port 0 and port 2 with eight individual bit programmable lines, and port 1 and port 3 with eight port programmable lines. you can connect pull-up or pull-down resistors to any or all of these lines on a bit by bit basis. you may want to pull lines up for connection to switches. this will pull the line high when the switch is open. or, you may want to pull lines down for connection to relays which control turning motors on and off. these motors turn on when the digital lines controlling them are high. by pulling these lines down, you can ensure that when the data acquisition system is first turned on, the motors will not switch on before the port is initialized. 10 k ohm pull-up/pull-down resistors are installed on the board, and jumpers are placed at the factory on p5, p6, p7 and p8 so that all 32 i/o lines are pulled up. each bit is labeled on the board. p5 connects to the resistors for port 2, p6 connects to the resistors for port 3, p7 connects to the resistors for port 0 and p8 connects to the resistors for port 1. the pins are labeled g (for ground) on one end and v (for +5v) on the other end. the middle pin is common. figure 1-7 shows these headers with the factory-installed jumpers, with the jumpers placed between the common pin (middle pin of the three) and the v pin (the left pin on each header). for pull-downs, install the jumper across the common pin (middle pin) and g pin (right pin on each header). to disable the pull- up/pull-down resistor, remove the jumper. 0 1 2 3 4 5 6 7 port 3 port 2 p5 p6 g v g v 0 1 2 3 4 5 6 7 port 1 port 0 p7 p8 g v g v fig. 1-7 ports 0, 1, 2 and 3 pull-up/pull-down resistor connections www.datasheet.co.kr datasheet pdf - http://www..net/
2-1 chapter 2 board installation the 3500 is easy to install in your pc/at or compatible computer. this chapter tells you step-by-step how to install and connect the board. after you have installed the board and made all of your con- nections, you can turn your system on and run the 3500diag board diagnostics program included on your example software disk to verify that your board is working. www.datasheet.co.kr datasheet pdf - http://www..net/
2-2 www.datasheet.co.kr datasheet pdf - http://www..net/
2-3 board installation keep the board in its antistatic bag until you are ready to install it in your computer. when removing it from the bag, hold the board at the edges and do not touch the components or connectors. before installing the board in your computer, check the jumper and switch settings. chapter 1 reviews the factory settings and how to change them. if you need to change any settings, refer to the appropriate instructions in chapter 1. note that incompatible jumper settings can result in unpredictable board operation and erratic response. to install the board: 1. turn off the power to your at computer. 2. remove the top cover of the computer housing (refer to your owners manual if you do not already know how to do this). 3. select any unused expansion slot and remove the slot bracket. 4. touch the metal housing of the computer to discharge any static buildup and then remove the board from its antistatic bag. 5. holding the board by its edges, orient it so that its card edge (bus) connectors line up with the expansion slot connectors in the bottom of the selected expansion slot. 6. after carefully positioning the board in the expansion slot so that the card edge connectors are resting on the computers bus connectors, gently and evenly press down on the board until it is secured in the slot. note: do not force the board into the slot. if the board does not slide into place, remove it and try again. wiggling the board or exerting too much pressure can result in damage to the board or to the computer. 7. after the board is installed, secure the slot bracket back into place and put the cover back on your computer. the board is now ready to be connected via the external i/o connector at the rear panel of your computer. be sure to observe the keying when connecting your external cable to the i/o connector. external i/o connections figure 2-1 shows the 3500s p3 & p4 50-pin i/o connector pinout. refer to these diagrams as you make your i/o connections. fig. 2-1 p3 & p4 i/o connector pin assignments 39 40 37 38 35 36 33 34 31 32 29 30 27 28 25 26 23 24 21 22 19 20 17 18 15 16 13 14 11 12 9 10 7 8 5 6 3 4 1 2 49 50 47 48 45 46 43 44 41 42 ain1- ain9 / agnd ain2- ain10 / agnd ain3- ain11 / agnd ain4- ain12 / agnd ain5- ain13 / agnd ain6- ain14 / agnd ain7- ain15 / agnd ain8- ain16 / agnd analog gnd analog gnd analog gnd p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 digital gnd ext gate 1 clk out1 / clk out2 ext gate 2 +5 volts digital gnd ain1+ ain2+ ain3+ ain4+ ain4+ ain6+ ain7+ ain8+ ain1 ain2 ain3 ain4 ain5 ain6 ain7 ain8 aout 1 aout 2 analog gnd p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 trigger in ext pacer clk clk out0 / dig irq ext clk +12 volts -12 volts diff. s.e. diff. s.e. 39 40 37 38 35 36 33 34 31 32 29 30 27 28 25 26 23 24 21 22 19 20 17 18 15 16 13 14 11 12 9 10 7 8 5 6 3 4 1 2 49 50 47 48 45 46 43 44 41 42 digital gnd digital gnd digital gnd digital gnd digital gnd digital gnd digital gnd digital gnd n.c. n.c. digital gnd p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 digital gnd n.c. n.c. n.c. +5 volts digital gnd n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. digital gnd p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 ext int n.c. n.c. n.c. +12 volts -12 volts www.datasheet.co.kr datasheet pdf - http://www..net/
2-4 connecting the analog input pins the 3500 provides flexible input connection capabilities to accommodate a wide range of sensors. you can mix single-ended, single-ended with dedicated ground, differential, and differential with a separate ground reference through a 10 kilohm resistor. single-ended and differential are software selectable; dedicated grounds and ground references are connected by setting the dip switches on s2 and s3 as described in chapter 1. figure 2-2 shows a general connection diagram. the following paragraphs describe how each type of connection can be made. single-ended, no dedicated gnd. to configure a single-ended analog input with no dedicated grounds, connect the high side of the input signal to the selected analog input channel, ain1 through ain16, and connect the low side to any of the analog gnd pins available at the connector (pins 18, 20-22 on p3). single-ended, dedicated gnd. to configure a single-ended analog input with dedicated ground, close the dip switch for the selected channel on s2, connect the high side of the input signal to the selected analog input channel, ain1 through ain8, and connect the low side to its corresponding agnd (ain1- through ain8-). the board is programmed for the single-ended, dedicated ground mode by setting up ba + 4, bit 9 for differential and grounding the negative side of the input signal. differential. for differential inputs, your signal source may or may not have a separate ground reference. when using the differential mode, you may need to close the selected channels dip switch on s3 to provide a reference to ground for a signal source without a separate ground reference. when you close a dip switch on s3, make sure that the corresponding dip switch on s2 is open, or the resistor will be bypassed. connect the high side of the analog input to the selected analog input channel, ain1+ through ain8+, and connect the low side to the corresponding ain- pin. then, for signal sources with a separate ground reference, connect the ground from the signal source to an analog gnd (pins 18 and 20-22 on p3). 3500 i/o connector p3 signal source 1 + - out pin 1 pin 2 signal source 8 + - out pin 15 pin 16 ain 1+ ain 1- ain 8+ ain 8- mux + - out + out - s2 s3 10k 10k 11 88 fig. 2-2 3500 input connection diagram www.datasheet.co.kr datasheet pdf - http://www..net/
2-5 connecting the analog outputs for each of the two d/a outputs, connect the high side of the device receiving the output to the aout channel (p3-17 or p3-19) and connect the low side of the device to an analog gnd (p3-18 or p3-20). connecting the timer/counters and digital i/o for all of these connections, the high side of an external signal source or destination device is connected to the appropriate signal pin on the i/o connector, and the low side is connected to any digital gnd. running the 3500diag diagnostics program now that your board is ready to use, you will want to try it out. an easy-to-use, menu-driven diagnostics program, 3500diag, is included with your example software to help you verify your boards operation. you can also use this program to make sure that your current base address setting does not contend with another device. www.datasheet.co.kr datasheet pdf - http://www..net/
2-6 www.datasheet.co.kr datasheet pdf - http://www..net/
3-1 chapter 3 hardware description this chapter describes the features of the AD3500 and ada3500 hardware. the major circuits are the a/d, the d/a, the timer/counters, and the digital i/o lines. www.datasheet.co.kr datasheet pdf - http://www..net/
3-2 www.datasheet.co.kr datasheet pdf - http://www..net/
3-3 the 3500 has four major circuits, the a/d, the d/a, the timer/counters, and the digital i/o lines. figure 3-1 shows the block diagram of the board. this chapter describes the hardware which makes up the major circuits. fig. 3-1 3500 block diagram a/d conversion circuitry the 3500 board performs analog-to-digital conversions on up to 16 software-selectable analog input channels. the following paragraphs describe the a/d circuitry. analog inputs the input voltage range is -10 to +10 volts. software programmable binary gains of 1, 2, 4, 8, 16, 32, 64, and 128 let you amplify lower level signals to more closely match the boards input ranges. overvoltage protection to 12 volts is provided at the inputs. fifo 1024 x 16 timer clk gate out pacer clock 8mhz osc address decode control 16 analog inputs -10v to +10v 8 diff./16 s.e./ 8 s.e. with agnd 3 address pc bus timer out i/o connector trigger in dma control and select clk 16-bit a/d converter mux channel / gain scan memory and control pacer clock and trigger control data interrupt select counter clk gate out digital i/o 16-bit d/a converter 12 volts +5 volts control ext pacer clk ext clock ext gate counter out p1.0 - 7 8 program- mable gain circuitry 1/2/4/8/16/g 16 high speed sample counter timer i/o select counter i/o select pull-up/down resistors p0.0 - 7 8 p3.0 - 7 8 p2.0 - 7 on-board connector aout 1 x 16-bit d/a converter aout 2 extgate2 extclk2 fifo 1024 x 16 fifo 1024 x 16 mux 8 8 8 4 event/match interrupt www.datasheet.co.kr datasheet pdf - http://www..net/
3-4 channel-gain scan memory the channel-gain scan memory lets you sample channels in any order, at high speeds, with a different gain on each channel. this 1024 x 24-bit memory supports complex channel-gain scan sequences, including digital output control. using the digital output control feature, you can control external input expansion boards such as the tmx32 to expand channel capacity up to 512 channels. when used, these control lines are output on port 1. when the digital lines are not used for this feature, they are available for other digital control functions. a skip bit is provided in the channel-gain data word to support different sampling rates on different channels. when this bit is set, no a/d conversion is performed on the selected channel. chapters 4 and 5 detail this feature. a/d converter the 16-bit successive approximation a/d converter accurately digitizes dynamic input voltages in 10 microseconds, for a maximum throughput rate of 100 khz. the converter ic contains a sample-and-hold ampli- fier, a 16-bit a/d converter, a 2.5-volt reference, a clock, and a digital interface to provide a complete a/d conversion function on a single chip. its low power cmos logic combined with a high precision, low noise design give you accurate results. conversions are controlled by software command, by pacer clock, by using triggers to start and stop sam- pling, or by the sample counter to acquire a specified number of samples. an on-board or external pacer clock can be used to control the conversion rate. conversion modes are described in chapter 5, a/d conversions . 1024 sample buffer a first in, first out (fifo) 1024 sample buffer helps your computer manage the high throughput rate of the a/ d converter by providing an elastic storage bin for the converted data. even if the computer does not read the data as fast as conversions are performed, conversions will continue until a fifo full flag is sent to stop the converter. the sample buffer does not need to be addressed when you are writing to or reading from it; internal address- ing makes sure that the data is properly stored and retrieved. all data accumulated in the sample buffer is stored intact until the pc is able to complete the data transfer. its asynchronous operation means that data can be written to or read from it at any time, at any rate. when a transfer does begin, the data first placed in the fifo is the first data out. data transfer the converted data can be transferred to pc memory in one of three ways. direct memory access (dma) transfer supports conversion rates of up to 100,000 samples per second. data also can be transferred using the programmed i/o mode or the interrupt mode. a special interrupt mode using a rep ins (repeat input string) instruction supports very high speed data transfers. by generating an interrupt when the fifos half full flag is set, a rep ins instruction can be executed, transferring data to pc memory and emptying the sample buffer at the maximum rate allowed by the data bus. the pc data bus is used to read and/or transfer data to pc memory. in the dma transfer mode, you can make continuous transfers directly to pc memory without going through the processor. the converted data is stored in a 16-bit word read at ba + 4. d/a converters (ada3500) the digital-to-analog (d/a) circuitry features two independent 16-bit analog output channels with output ranges of -10 to +10 volts. each channel has it's own 1024 sample buffer for data storage before being output. data can be continuosly written to the buffer producing a non-repetetive output waveform or a set of data can be written into the buffer and continuosly cycled to produce a repeating waveform. data can be written into the output buffers by i/o instruction or by dma transfer. updating of the analog outputs can be done through software or by several different clocks and triggers. the outputs can be updated simultaneously or independently. www.datasheet.co.kr datasheet pdf - http://www..net/
3-5 fig. 3-2 timer/counter circuit block diagram clocktcu50 counter 0 clk gate out counter 1 clk gate out counter 2 clk gate out 8mhz 16-bit pacer clock pacer clock gate control 32-bit pacer clock burst clock gate control burst clock counter1 tc u51 counter 0 clk gate out counter 1 clk gate out counter 2 clk gate out +5 v +5 v +5 v sample count clock sample count delay count clock delay count dac2 count clock dac2 count 3500 i/o connector p3 ext pclk pin 44 ext gate 1 ext clk user tc u53 counter 0 clk gate out counter 1 clk gate out counter 2 clk gate out 8mhz pin 45 pin 41 pin 42 pin 46 ext gate 2 +5 v p10 dig int 1 p9 counter2 tc u52 counter 0 clk gate out counter 1 clk gate out counter 2 clk gate out +5 v +5 v +5 v 8mhz dac1 clock 8mhz dac2 clock dac1 count clock dac1 count pin 43 dig int 2 www.datasheet.co.kr datasheet pdf - http://www..net/
3-6 timer/counters four 8254 programmable interval timers provide twelve 16-bit, 8-mhz timer/counters to support a wide range of timing and counting functions. figure 3-2 shows the timer/counter block diagram. the 8254 at u50 is the clock tc. two of its 16-bit timer/counters, counter 0 and counter 1, are cascaded and reserved for the pacer clock. the pacer clock is described in chapter 5. the third timer/counter in the clock tc, counter 2, is the burst clock. the 8254 at u51 is the counter1 tc. counter 0 is the a/d sample counter, counter 1 is the a/d delay counter, and counter 2 is the d/a 2 sample counter. the 8254 at u52 is the counter2 tc. counter 0 is the d/a 1 clock, counter 1 is the d/a 2 clock, and counter 2 is the d/a 1 sample counter. the 8254 at u53 is the user tc. all three counters on this chip are available for user functions. each 16-bit timer/counter has two inputs, clk in and gate in, and one output, timer/counter out. each can be programmed as binary or bcd down counters by writing the appropriate data to the command word, as described in chapter 4. the command word also lets you set up the mode of operation. the six programmable modes are: mode 0 event counter (interrupt on terminal count) mode 1 hardware-retriggerable one-shot mode 2 rate generator mode 3 square wave mode mode 4 software-triggered strobe mode 5 hardware triggered strobe (retriggerable) these modes are detailed in the 8254 data sheet, reprinted from intel in appendix c. digital i/o the 32 digital i/o lines can be used to transfer data between the computer and external devices. sixteen lines are bit programmable and sixteen lines are byte, or port, programmable. port 0 and port 2 each provide eight bit programmable lines which can be independently set for input or output. these ports support rtds two advanced digital interrupt modes. an interrupt can be generated when the lines match a programmed value or when any bit changes its current state. a mask register lets you monitor selected lines for interrupt generation. port 1 and port 3 can each be programmed as an 8-bit input or output port. chapter 10 details digital i/o operations and chapter 7 explains digital interrupts. www.datasheet.co.kr datasheet pdf - http://www..net/
4-1 chapter 4 i/o mapping this chapter provides a complete description of the i/o map for the AD3500 and ada3500, general programming information, and how to set and clear bits in a port. www.datasheet.co.kr datasheet pdf - http://www..net/
4-2 www.datasheet.co.kr datasheet pdf - http://www..net/
4-3 defining the i/o map the i/o map for the AD3500 and ada3500 is shown in table 4-1 below. as shown, the board occupies 32 consecutive i/o port locations. because of the 16-bit structure of the at bus, every other address location is used. our programming struc- ture uses the 16-bit command for reading/writing all locations except for programming the 8254 and digital lines. these require 8-bit read/write operations. the base address (designated as ba) can be selected using dip switch s1, located on the top edge of the board as described in chapter 1, board settings . this switch can be accessed without removing the board from the computer. the following sections describe the register contents of each address used in the i/o map. table 4-1 AD3500/ada3500 i/o map register description read function write function address * (decimal) clear / clear mask register clears board circuits programmed by a write to this address sets the board circuits to be cleared ba + 0 read board status / set control register read board status word program 3500 control register ba + 2 read converted data / load channel-gain data read 16-bit converted data load channel & gain; load a/d & digital data into channel-gain table ba + 4 start convert / set trigger modes software start convert program triggers and clocks ba + 6 initialize dac sample counter/irq source & channel provides a software trigger to load dac sample counter select irq sources and channels ba + 8 update dacs/dac configuration register update d/a converter outputs program dac1 and dac2 configuration (ada3500) ba + 10 initialize a/d delay counter/d/a converter 1 provides software trigger to load a/d delay counter load dac1 fifo (ada3500) ba + 12 initialize a/d sample counter/d/a converter 2 provides software trigger to load a/d sample counter load dac2 fifo (ada3500) ba + 14 8254 tc counter 0 (tc selected at ba + 2) read value in tc counter 0 load count in tc counter 0 ba + 16 8254 tc counter 1 (tc selected at ba + 2) read value in tc counter 1 load count in tc counter 1 ba + 18 8254 tc counter 2 (tc selected at ba + 2) read value in tc counter 2 load count in tc counter 2 ba + 20 8254 tc control word (tc selected at ba + 2) reserved program counter mode for tc ba + 22 digital i/o port 0 (bit programmable) read port 0 or port 2 digital input lines program port 0 or port 2 digital output lines ba + 24 digital i/o port 1 (port programmable) read port 1 or port 3 digital input lines program port 1 or port 3 digital output lines ba + 26 port 0 clear/ direction/mask/compare clear digital irq status flag/read port 0 direction, mask or compare register (dependent on ba + 30) clear digital chip/program port 0 direction, mask or compare register (dependent on ba + 30) ba + 28 read digital i/o status/ set digital control register read digital status word program digital control register & digital interrupt enable ba + 30 * ba = base address www.datasheet.co.kr datasheet pdf - http://www..net/
4-4 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 xxx ba + 0: clear/program clear register (read/write) 16-bit operation. a read clears selected circuits on the board, depending on the value programmed at this same address, as described in the following paragraph. clear register: the value programmed in this register determines which clear, enable, and reset operations are carried out when a read at ba + 0 is executed. setting a bit high clears or enables the defined operation. this registers bits are described below: bit 0 C when high (bit 0 = 1), clears, or resets, the board. resets the board and initializes the a/d converter. bit 1 C when high (bit 1 = 1), clears the sample buffer. empties out all data in the fifo, sets the fifo empty flag low (ba + 2, bit 0) and clears the halt flag (ba + 2, bit 1), enabling a/d conversions. bit 2 C when high (bit 2 = 1), clears the a/d dma done flag at ba + 2, bit 2. bit 3 C when high (bit 3 = 1), clears the dac1 dma done flag at ba + 2, bit 14. bit 4 C when high (bit 4 = 1), clears the dac2 dma done flag at ba + 2, bit 15. bit 5 C when high (bit 5 = 1), clears the channel-gain table. erases the data entered into the channel-gain table. bit 6 C when high (bit 6 = 1), resets the channel-gain table. resets the channel-gain tables starting point to the beginning of the table. bit 7 C reserved. bit 8 C reserved. bit 9 C reserved. bit 10 C when high (bit 10 = 1), clears the irq1 request and status bit. bit 11 C when high (bit 11 = 1), clears the irq2 request and status bit. bit 12 C when high (bit 12 = 1), clears the dac1 fifo. bit 13 C when high (bit 13 = 1), clears the dac2 fifo. bit 14 C when high (bit 14 = 1), resets the dac1 fifo pointer to the beginning of the fifo. bit 15 C when high (bit 15 = 1), resets the dac2 fifo pointer to the beginning of the fifo. for example, if you want to clear the fifo and dma done flag, you would write a 6 to this address to set bits 1 and 2 high, followed by a read to carry out the clear operation. clear fifo and dma done flag (value written = 6): clear board 0 = no clear 1 = clear clear a/d fifo 0 = no clear 1 = clear clear a/d dma done flag 0 = no clear 1 = clear clear channel-gain table 0 = no clear 1 = clear clear d/a 1 dma done flag 0 = no clear 1 = clear reset channel-gain table 0 = no reset 1 = reset reset dac2 fifo 0 = no reset 1 = reset reset dac1 fifo 0 = no reset 1 = reset clear dac2 fifo 0 = no clear 1 = clear clear dac1 fifo 0 = no clear 1 = clear irq2 clear 0 = no clear 1 = clear irq1 clear 0 = no clear 1 = clear clear d/a 2 dma done flag 0 = no clear 1 = clear d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0000000000000110 www.datasheet.co.kr datasheet pdf - http://www..net/
4-5 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x ba + 2: read status/program control register (read/write) 16-bit operation. status register: a read provides the status bits defined below. starting with bit 0, these status bits show: bit 0 C goes high when there is something in the a/d sample buffer (fifo). bit 1 C goes high and halts a/d conversions when the sample buffer is full (this is useful whenever you are emptying the buffer at a slower rate than you are taking data). a clear fifo written to ba + 0 (bit 1 set high) clears the sample buffer and this flag. bit 2 C goes high when an a/d dma transfer is completed (active in dma mode only). bit 3 C goes high when the dma transfer for the first channel (set at ba + 2, bits 13 and 12) is complete. this flag is used in dual channel dma mode to signal when the switch is made to the second channel. dual channel dma transfer is explained in more detail in chapter 6, dma transfers . bit 4 C shows the status of the burst clock gate (useful when using external triggering). bit 5 C shows the status of the pacer clock gate (useful when using external triggering). bit 6 C shows the start convert delay status. goes high when the delay is over and sampling has started. bit 7 C shows the stop convert about trigger status. goes high after the about trigger has occurred. bit 8 C shows when an advanced digital mode interrupt has occurred. in this manual, the term digital interrupt specifically refers to an interrupt generated by the bit programmable digital i/o port 0 advanced digital interrupt circuitry. bit 9 C reserved. bit 10 C this bit is low when the dac 1 fifo is empty. bit 11 C this bit is low when the dac 2 fifo is empty. bit 12 C this bit is low when the dac 1 fifo is full. bit 13 C this bit is low when the dac 2 fifo is full. bit 14 C goes high when a dac1 dma transfer is completed (active in dma mode only). bit 15 C goes high when a dac2 dma transfer is completed (active in dma mode only). a/d fifo empty flag 0 = fifo empty 1 = fifo not empty a/d dma done flag 0 = dma not done 1 = dma done first dma flag (for dual channel dma) 0 = dma not done on first channel 1 = dma done on first channel a/d halt flag 0 = a/d enabled 1 = a/d disabled burst clock gate flag 0 = burst gate off 1 = burst gate on pacer clock gate flag 0 = pacer clock off 1 = pacer clock on dac2 fifo empty 0 = fifo empty 1 = fifo not empty dac1 fifo full 0 = fifo full 1 = fifo not full dac2 fifo full 0 = fifo full 1 = fifo not full dac1 dma done flag 0 = dma not done 1 = dma done dac2 dma done flag 0 = dma not done 1 = dma done digital irq status 0 = no digital irq 1 = digital irq about trigger flag 0 = in progress 1 = completed dac1 fifo empty 0 = fifo empty 1 = fifo not empty delay status 0 = delay not over 1 = delay over www.datasheet.co.kr datasheet pdf - http://www..net/
4-6 control register: a write to ba + 2 sets up the control register shown above: bits 0 and 1 C the setting of these bits determines where the data written at ba + 4 is stored. when bits 1 and 0 are 00, channel-gain data is loaded into the channel-gain latch. when bits 1 and 0 are 01, channel-gain data is loaded into the a/d table of the channel-gain scan memory. when bits 1 and 0 are 10, digital data is loaded into the digital table of the channel-gain scan memory. bits 2 and 3 C these bits are used to enable/disable the a/d and digital tables in the channel-gain scan memory. when bits 3 and 2 are 00, the channel-gain scan memory is disabled and the data written to the channel-gain latch will be used for a/d conversions. when bits 3 and 2 are 01, the a/d table in the channel-gain scan memory is activated to be used for a/d conversions. when bits 3 and 2 are 11, both the a/d and digital tables in the channel-gain scan memory are activated to be used for a/d conver- sions. note that while you can enable, disable, and then re-enable the channel-gain table in the middle of taking a set of data, it is not recommended that you do this. one entry in the table is skipped each time the table is disabled and re-enabled unless reset table at ba + 0 is used to reset the table pointer. bit 4 C when enabled, the 16-bit channel-gain table entry for each conversion is stored in the sample buffer along with the converted data. the order of storage in the buffer is channel-gain table data, followed by the converted data. bits 5 and 6 C selects the 8254 timer/counter to be programmed at ba + 16 through ba + 22. the clock tc is the pacer clock/burst clock timer; the counter1 tc is the a/d sample counter, a/d delay counter, and d/a 2 sample counter; the counter2 tc is the dac 1 & 2 clocks and d/a 1 sample counter;and the user tc is the user timer/counter. bit 7 C when enabled (set to 0), the a/d sample counter counts down once and stops the pacer clock. when disabled (set to 1), the a/d sample counter repeats the countdown until you enable the stop bit (set this bit to 0). chapter 5 explains how to use this bit for sample counts greater than 65,536 (the size of the 16-bit a/d sample counter). bit 8 C when enabled (set to 0), the pause bit in the a/d table in the channel-gain scan memory (ba + 4, bit 10) is activated. when disabled, the pause bit setting at ba + 4 is ignored. bit 9 C selects the digital i/o chip to be programmed at ba + 24 through ba + 30. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 channel-gain load 00 = load channel-gain latch 01 = load a/d table 10 = load digital table 11 = reserved a/d & digital channel- gain table enable 00 = both tables disabled 01 = a/d table enabled 10 = reserved 11 = both tables enabled channel-gain data store 0 = disabled 1 = enabled a/d dma2 channel select 00 = disabled 01 = drq5 10 = drq6 11 = drq7 dio chip select 0 = chip 1 1 = chip 2 a/d dma1 channel select 00 = disabled 01 = drq5 10 = drq6 11 = drq7 pacer clock size 0 = 16-bit 1 = 32-bit trigger polarity 0 = positive edge 1 = negative edge ba + 14 through 22 timer/counter select 00 = clock tc 01 = counter1 tc 10 = counter2 tc 11 = user tc a/d sample counter stop enable 0 = enabled 1 = disabled pause enable 0 = enabled 1 = disabled www.datasheet.co.kr datasheet pdf - http://www..net/
4-7 bit 10 C selects a 16-bit or 32-bit on-board pacer clock (clock tc counter 0 or 1 output). when a trigger is used to start the pacer clock, there is some delay between the time the trigger occurs and the time the next pacer clock pulse starts an a/d conversion. for a 16-bit clock, this jitter is 250 nanoseconds maximum. however, a 32-bit clocks jitter is dependent on the value programmed into the first divider and can be much greater than 250 nanoseconds. (see chapter 5.) bit 11 C sets the external trigger to occur on the positive-going or negative-going edge of the pulse. bits 12 through 15 are used to set the drq channels for a/d dma transfer. for simple dma transfers using one channel, select the channel on bits 12 and 13. when using dual channels in the autoinitialized dma mode (dma controller autoinitialized so that you can flip-flop transfers, see chapter 6) for large transfers, you must select different channels for dma1 and dma2. ba + 4: read converted data/load channel-gain & digital data (read/write) 16-bit data word read from fifo (16-bit operation): (msb) (lsb) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 bit 16 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 a read provides the 16-bit a/d converted data as shown above. readings are in twos complement format. if the channel-gain data store bit at ba + 2, bit 4 is enabled, the first read at this address provides the 16-bit channel-gain table entry, and is followed by a second read to provide the converted data. chapter 5 details how readings are taken when using the channel-gain data store feature. load channel-gain latch (ba + 2, bits 1 and 0 = 00) (16-bit operation): d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 000000 00 analog input channel select 0000 = channel 1 0001 = channel 2 0010 = channel 3 0011 = channel 4 0100 = channel 5 0101 = channel 6 0110 = channel 7 0111 = channel 8 1000 = channel 9 1001 = channel 10 1010 = channel 11 1011 = channel 12 1100 = channel 13 1101 = channel 14 1110 = channel 15 1111 = channel 16 a/d se/diff 0 = single-ended 1 = differential gain select 000 = x 1 001 = x 2 010 = x 4 011 = x 8 100 = x 16 101 = x 32 110 = x 64 111 = x 128 to load channel and gain for conversions not using the channel-gain table: first, make sure that bits 1 and 0 at ba + 2 are set to 00. then write the desired channel and gain information to ba + 4. bit 9 selects whether the input is single-ended or differential. www.datasheet.co.kr datasheet pdf - http://www..net/
4-8 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0000 00 load a/d table in channel-gain scan memory (ba + 2, bits 1 and 0 = 01) (16-bit operation): analog input channel select 0000 = channel 1 0001 = channel 2 0010 = channel 3 0011 = channel 4 0100 = channel 5 0101 = channel 6 0110 = channel 7 0111 = channel 8 1000 = channel 9 1001 = channel 10 1010 = channel 11 1011 = channel 12 1100 = channel 13 1101 = channel 14 1110 = channel 15 1111 = channel 16 a/d se/diff 0 = single-ended 1 = differential to load the a/d portion of the channel-gain table with channel and gain information: first, set bits 1 and 0 at ba + 2 to 01 to enable loading of channel and gain data into the a/d portion of the channel-gain table. then, load the data in the format shown above. each write fills the next position in the channel-gain table. using the pause bit: the pause bit at bit 10 of the channel-gain word is set to 1 if you want to stop at an entry in the table and wait for the next trigger to resume conversions. in burst mode, the pause bit is ignored. using the skip bit: the skip bit at bit 11 of the channel-gain word is set to 1 if you want to skip an entry in the table. this feature allows you to sample multiple channels at different rates on each channel. for example, if you want to sample channel 1 once each second and channel 4 once every 3 seconds, you can set the skip bit on channel 4 as shown in figure 4-1. with the skip bit set on the four table entries as shown, these entries will be ignored, and no a/d conversion will be performed. this saves memory and eliminates the need to throw away unwanted data. pause bit 0 = disabled 1 = enabled skip bit 0 = disabled 1 = enabled pacer clock a/d conversion 11141114 1 sec channel sampled 1 4 skip 1 4 skip 1 4 1 4 skip 1 4 skip 1 4 3 sec 1 sec 1 sec 1 sec 1 sec fig. 4-1 using the skip bit gain select 000 = x 1 001 = x 2 010 = x 4 011 = x 8 100 = x 16 101 = x 32 110 = x 64 111 = x 128 www.datasheet.co.kr datasheet pdf - http://www..net/
4-9 load digital table in channel-gain scan memory (ba + 2, bits 1 and 0 = 10) (8-bit operation): tmx32 channel select 00000 = channel 1 00001 = channel 2 ? 11111 = channel 32 to load the digital portion of the channel-gain table with digital information: the digital portion of the channel-gain table provides 8 bits to control devices such as external expansion boards. for example, if you have connected one of your input channels on the 3500 to rtds tmx32 input expansion board, you can use the bottom 5 bits in this byte to control the tmx32 board channel selection. to load digital information into this portion of the channel-gain table, set bits 1 and 0 at ba + 2 to 10 to enable loading of the digital portion of the channel-gain table. then, load the data, setting 0s and 1s as needed by whatever you are controlling. this information will be output on the port 1 lines when you run through the table. the format shown above is for controlling the tmx32s channel selection (32 single-ended or 16 differential). the first load operation will be in the first entry slot of the table (lining up with the first entry in the a/d table), and each load thereafter fills the next position in the channel-gain table. note that when you are using the digital table, all 8 bits are used and controlled by the table, regardless of the number of bits you may actually need for your digital control application. ba + 6: start convert/program trigger modes (read/write) 16-bit operation. a read at this address issues a start convert command (software trigger). trigger mode register: p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 start trigger select 0000 = software trigger 0001 = external trigger 0010 = digital interrupt 0011 = user tc counter 2 out 0100 = reserved 0101 = reserved 0110 = reserved 0111 = reserved 1000 = delayed software trigger 1001 = delayed external trigger 1010 = delayed digital interrupt 1011 = delayed user tc 1100 = reserved 1101 = reserved 1110 = reserved 1111 = gate mode conversion select 000 = software trigger 001 = pacer clock 010 = burst clock 011 = digital interrupt 100 = reserved 101 = reserved 110 = reserved 111 = reserved stop trigger select 0000 = software trigger 0001 = external trigger 0010 = digital interrupt 0011 = sample counter 0100 = reserved 0101 = reserved 0110 = reserved 0111 = reserved 1000 = about software trigger 1001 = about external trigger 1010 = about digital interrupt 1011 = about user tc counter 2 out 1100 = reserved 1101 = reserved 1110 = reserved 1111 = reserved burst trigger select 000 = software trigger 001 = pacer clock 010 = external trigger 011 = digital interrupt 100 = reserved 101 = reserved 110 = reserved 111 = reserved trigger repeat 0 = single cycle 1 = repeat cycle pacer clock select 0 = internal 1 = external www.datasheet.co.kr datasheet pdf - http://www..net/
4-10 this register sets up the method by which a/d conversions are performed (conversion select bits) and the trigger mode. trigger mode register, performing a/d conversions (bits 0 through 2): 000 = conversions are controlled by reading ba + 6 (start convert). 001 = conversions are controlled by the internal or an external pacer clock. 010 = conversions are controlled by the burst clock. 011 = conversions are controlled by a digital interrupt. 100 = reserved. 101 = reserved. 110 = reserved. 111 = reserved. trigger mode register, selecting the start trigger source (bits 3 through 6): 0000 = the pacer clock is started by reading ba + 6 (start convert). 0001 = the pacer clock is started by an external trigger (trigger in, p3-39). 0010 = the pacer clock is started by a digital interrupt. 0011 = the pacer clock is started when the output of user tc counter 2 reaches 0. 0100 = reserved. 0101 = reserved. 0110 = reserved. 0111 = reserved. the following start trigger sources provide delayed triggering. when the trigger is issued, the a/d delay counter, counter1 tc, counter 1, counts down and conversions are started when the a/d delay counter reaches 0. the a/d delay counter counts at the pacer clock rate. 1000 = the a/d delay counter is started by reading ba + 6 (start convert). 1001 = the a/d delay counter is started by an external trigger (trigger in, p3-39). 1010 = the a/d delay counter is started by a digital interrupt. 1011 = the a/d delay counter is started when the output of user tc counter 2 reaches 0. 1100 = reserved. 1101 = reserved. 1110 = reserved. 1111 = gate mode: the pacer clock runs as long as the trigger in line is held high or low, depending on the polarity bit setting at ba + 2, bit 11. this mode does not use a stop trigger. trigger mode register, selecting the stop trigger source (bits 7 through 10): 0000 = the pacer clock is stopped by reading ba + 6 (start convert). 0001 = the pacer clock is stopped by an external trigger (trigger in, p3-39). 0010 = the pacer clock is stopped by a digital interrupt. 0011 = the pacer clock is stopped by the sample counter (count reaches 0). 0100 = reserved. 0101 = reserved. 0110 = reserved. 0111 = reserved. the following stop trigger sources programmed at these bits provide about triggering, where data is acquired from the time the start trigger is received, and continues for a specified number of samples after the stop trigger is received. the number of samples taken after the stop trigger is received is set by the a/d sample counter. 1000 = the a/d sample counter takes a specified number of samples after a read at ba + 6 (start convert). 1001 = the a/d sample counter takes a specified number of samples after an external trigger is received. 1010 = the a/d sample counter takes a specified number of samples after a digital interrupt occurs. 1011 = the a/d sample counter takes a specified number of samples after the output of user tc counter 2 reaches 0. www.datasheet.co.kr datasheet pdf - http://www..net/
4-11 1100 = reserved. 1101 = reserved 1110 = reserved. 1111 = reserved. trigger mode register, bits 11 through 15: bits 11, 12 and 13 C select the burst mode trigger. bursts can be triggered through software (start convert command), by the pacer clock, by an external trigger, or by a digital interrupt. bit 14 C selects the internal pacer clock, which is the output of clock tc counter 0 or 1, or an external pacer clock routed onto the board through p3-41. the maximum pacer clock rate supported by the board is 100 khz. bit 15 C when set to single cycle, a trigger will initiate one conversion cycle and then stop, regardless of whether the trigger line is pulsed more than once; when set to repeat, a new cycle will start each time a trigger is received, and the current cycle has been completed. triggers received while a cycle is in progress will be ignored. ba + 8: load dac sample counter/program irq source & channel (read/write) 16-bit operation. a read provides a software trigger so that the dac sample counter can be loaded with the correct value. this software correction is used as an easy means to compensate for the operating structure of the 8254. two pulses of the counter are required to actually load the desired count and prepare the counter to count down correctly (this can be looked at as the initialization procedure for the dac sample counter). a pulse is sent to the dac sample counter (counter tc counter 2) each time you read this address. without this correction, the initial count sequence will be off by two pulses. once the counter is properly loaded and starts, any subsequent countdowns of this count will be accurate. you must select which dac sample counter to load by selecting the proper 8254 chip a register ba + 2. note that the dac sample counter must be programmed for mode 2 opera- tion. interrupt register: irq1 source select 00000 = a/d sample counter 00001 = a/d start convert 00010 = a/d fifo half-full 00011 = a/d dma done 00100 = reset channel-gain table 00101 = pause channel-gain table 00110 = external pacer clock 00111 = external trigger 01000 = dac1 sample counter 01001 = dac2 sample counter 01010 = dac1 dma done 01011 = dac2 dma done 01100 = digital interrupt 1 01101 = user tc counter 1 out 01110 = user tc counter 1 out inverted 01111 = user tc counter 2 out 10000 = reserved 10001 = reserved 10010 = reserved 10011 = reserved 10100 = external interrupt 10101 = digital interrupt 2 10110 - 11111 = reserved irq1 channel select 000 = disabled 001 = irq3 010 = irq5 011 = irq9 100 = irq10 101 = irq11 110 = irq12 111 = irq15 irq2 source select 00000 = a/d sample counter 00001 = a/d start convert 00010 = a/d fifo half-full 00011 = a/d dma done 00100 = reset channel-gain table 00101 = pause channel-gain table 00110 = external pacer clock 00111 = external trigger 01000 = dac1 sample counter 01001 = dac2 sample counter 01010 = dac1 dma done 01011 = dac2 dma done 01100 = digital interrupt 1 01101 = user tc counter 1 out 01110 = user tc counter 1 out inverted 01111 = user tc counter 2 out 10000 = reserved 10001 = reserved 10010 = reserved 10011 = reserved 10100 = external interrupt 10101 = digital interrupt 2 10110 - 11111 = reserved irq2 channel select 000 = disabled 001 = irq3 010 = irq5 011 = irq9 100 = irq10 101 = irq11 110 = irq12 111 = irq15 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 www.datasheet.co.kr datasheet pdf - http://www..net/
4-12 this register programs the software selectable interrupt source and channel. the irq circuitry is driven by an open collector device which is turned off when the irq channel is set to disable. the irq sources are described below: a/d sample counter - an interrupt is generated when the a/d sample counter count reaches 0. a/d start convert - an interrupt is generated when a conversion is started. a/d fifo half full - an interrupt is generated when the a/d fifo is half-full. a/d dma done - an interrupt is generated when the a/d dma done flag goes high. reset channel-gain table - an interrupt is generated when the channel-gain table resets to the beginning. pause channel-gain table - an interrupt is generated when a pause occurs in the channel-gain table. external pacer clock - an interrupt is generated when the external pacer clock line is pulsed. external trigger - an interrupt is generated when the external trigger line is pulsed. dac1 sample counter - an interrupt is generated when the dac1 sample counter reaches 0. dac2 sample counter - an interrupt is generated when the dac2 sample counter reaches 0. dac1 dma done - an interrupt is generated when the dac1 dma done flag goes high. dac2 dma done - an interrupt is generated when the dac2 dma done flag goes high. digital interrupt 1 - an interrupt is generated by the first digital i/o chip. user tc counter 1 out - an interrupt is generated when user tc counter 1s count reaches 0. user tc counter 1 out inverted - an interrupt is generated when user tc counter 1s count reaches 0 (useful for frequency counting). user tc counter 2 out - an interrupt is generated when user tc counter 2s count reaches 0. external interrupt - an interrupt is generated when the external interrupt line is pulsed. digital interrupt 2 - an interrupt is generated by the second digital i/o chip. ba + 10: update dac/program dac configuration register (read/write) 16-bit operation. a read updates the dac outputs. when the board is reset, the dac outputs go to zero. dac configuration register: this register is used to configure the d/a output channels, dac1 and dac2, on the ada3500 as follows: bits 0 and 1 C reserved. bits 2, 3 and 4 C these bits select the update source for dac 1. software uses the software command (read at ba + 10) to update the dac1 output; the a/d clock is used to synchronize the dac output to the a/d conversions; user tc out 2 uses the output of user tc, counter 2; dac1 clock uses the output of counter2 tc, counter 0; dac2 clock uses the output of counter2 tc, counter 1; external pacer clock uses the signal at p3 pin 41; external trigger uses the signal at p3 pin 39; and disable shuts off the update to the d/a converter. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 00 00 dac2 dma channel select 00 = disabled 01 = drq5 10 = drq6 11 = drq7 dac1 dma channel select 00 = disabled 01 = drq5 10 = drq6 11 = drq7 dac2 update select 000 = software 001 = a/d clock 010 = user tc out 2 011 = dac1 clock 100 = dac2 clock 101 = external pacer clock 110 = external trigger 111 = disabled dac1 update select 000 = software 001 = a/d clock 010 = user tc out 2 011 = dac1 clock 100 = dac2 clock 101 = external pacer clock 110 = external trigger 111 = disabled dac2 cycle 0 = not cycle 1 = cycle dac1 cycle 0 = not cycle 1 = cycle www.datasheet.co.kr datasheet pdf - http://www..net/
4-13 bits 5 and 6 C reserved. bits 7, 8 and 9 C these bits select the update source for dac 2. software uses the software command (read at ba + 10) to update the dac2 output; the a/d clock is used to synchronize the dac output to the a/d conversions; user tc out 2 uses the output of user tc, counter 2; dac1 clock uses the output of counter2 tc, counter 0; dac2 clock uses the output of counter2 tc, counter 1; external pacer clock uses the signal at p3 pin 41; external trigger uses the signal at p3 pin 39; and disable shuts off the update to the d/a converter. bits 10 and 11 C these bits enable the cycle mode for the d/a converters. by setting these bits to a 1, the d/ a will cotinuously repeat the data that is stored in the dac fifo.this is useful for waveform generation. bits 12 through 15 C these bits select the dma channel for transfers on the dac's. if you are using a/d and d/a dma, you must make sure that you select a different dma channel for the a/d, dac1 and dac2. when these bits are set to 0, the dma channels are disabled. ba + 12: load a/d delay counter/d/a converter 1 data (read/write) 16-bit operation. a read provides a software trigger so that the a/d delay counter can be loaded with the correct value. this software correction is used as an easy means to compensate for the operating structure of the 8254. two pulses of the counter are required to actually load the desired count and prepare the counter to count down correctly (this can be looked at as the initialization procedure for the a/d delay counter). a pulse is sent to the a/d delay counter (counter1 tc counter 1) each time you read this address. without this correction, the initial count sequence will be off by two pulses. once the counter is properly loaded and starts, any subsequent countdowns of this count will be accurate. note that the a/d delay counter must be programmed for mode 2 operation. dac1 output: a write programs the dac1 16-bit output in the format shown above. output coding is two's complement. ba + 14: load a/d sample counter/d/a converter 2 data (read/write) 16-bit operation. a read provides a software trigger so that the a/d sample counter can be loaded with the correct value. this software correction is used as an easy means to compensate for the operating structure of the 8254. two pulses of the counter are required to actually load the desired count and prepare the counter to count down correctly (this can be looked at as the initialization procedure for the a/d sample counter). a pulse is sent to the a/d sample counter (counter1 tc counter 0) each time you read this address. without this correction, the initial count sequence will be off by two pulses. once the counter is properly loaded and starts, any subsequent countdowns of this count will be accurate. note that the a/d sample counter must be programmed for mode 2 operation. dac2 output: d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (msb) (lsb) a write programs the dac2 16-bit output in the format shown above. output coding is two's complement. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (msb) (lsb) www.datasheet.co.kr datasheet pdf - http://www..net/
4-14 ba + 16: tc counter 0 (read/write) 8-bit operation. a write loads the first counter in one of the four timer/counters on the board with a new 16-bit value in two 8-bit steps, lsb followed by msb. the counter must be loaded in two 8-bit steps! counting begins as soon as the count is loaded. the timer/counter being loaded is selected by writing to ba + 2, bits 5 and 6. a read shows the count in the counter. ba + 18: tc counter 1 (read/write) 8-bit operation. a write loads the second counter in one of the four timer/counters on the board with a new 16-bit value in two 8-bit steps, lsb followed by msb. the counter must be loaded in two 8-bit steps! counting begins as soon as the count is loaded. the timer/counter being loaded is selected by writing to ba + 2, bits 5 and 6. a read shows the count in the counter. ba + 20: tc counter 2 (read/write) 8-bit operation. a write loads the third counter in one of the four timer/counters on the board with a new 16-bit value in two 8-bit steps, lsb followed by msb. the counter must be loaded in two 8-bit steps! counting begins as soon as the count is loaded. the timer/counter being loaded is selected by writing to ba + 2, bits 5 and 6. a read shows the count in the counter. ba + 22: timer/counter control word (write only) 8-bit operation. accesses the selected timer/counters control register to directly control the three 16-bit counters, 0, 1, and 2. ba + 24: digital i/o port 0 (port 2), bit programmable port (read/write) 8-bit operation. port 0: d7 d6 d5 d4 d3 d2 d1 d0 counter select 00 = counter 0 01 = counter 1 10 = counter 2 11 = read back setting counter mode select 000 = mode 0, event count 001 = mode 1, programmable 1-shot 010 = mode 2, rate generator 011 = mode 3, square wave rate generator 100 = mode 4, software-triggered strobe 101 = mode 5, hardware-triggered strobe read/load 00 = latching operation 01 = read/load lsb only 10 = read/load msb only 11 = read/load lsb, then msb bcd/binary 0 = binary 1 = bcd this port transfers the 8-bit port 0 bit programmable digital input/output data between the board and external devices. the bits are individually programmed as input or output by writing to the direction register at ba + 28. for all bits set as inputs, a read reads the input values and a write is ignored. for all bits set as outputs, a read reads the last value sent out on the line and a write writes the current loaded value out to the line. note that when any reset of the digital circuitry is performed (clear chip or computer reset), all digital lines are reset to inputs and their corresponding output registers are cleared. d7 d6 d5 d4 d3 d2 d1 d0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 www.datasheet.co.kr datasheet pdf - http://www..net/
4-15 ba + 26: digital i/o port 1 (port 3), byte programmable port (read/write) 8-bit operation. port 1: d7 d6 d5 d4 d3 d2 d1 d0 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.1 this port transfers the 8-bit port 1 digital input or digital output byte between the board and an external device. when port 1 is set as inputs, a read reads the input values and a write is ignored. when port 1 is set as outputs, a read reads the last value sent out of the port and a write writes the current loaded value out of the port. note that when any reset of the digital circuitry is performed (clear chip or computer reset ), all digital lines are reset to inputs and their corresponding output registers are cleared. ba + 28: read/program port 0 (port 2) direction/mask/compare registers (read/write) 8-bit operation. a read clears the irq status flag or provides the contents of one of digital i/o port 0s three control registers; and a write clears the digital chip or programs one of the three control registers, depending on the setting of bits 0 and 1 at ba + 30. when bits 1 and 0 at ba + 30 are 00, the read/write operations clear the digital irq status flag (read) and the digital chip (write). when these bits are set to any other value, one of the three port 0 registers is addressed. direction register (ba + 30, bits 1 and 0 = 01): d7 d6 d5 d4 d3 d2 d1 d0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 for all bits: 0 = input 1 = output this register programs the direction, input or output, of each bit at port 0. mask register (ba + 30, bits 1 and 0 = 10): d7 d6 d5 d4 d3 d2 d1 d0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 for all bits: 0 = bit enabled 1 = bit masked in the advanced digital interrupt modes, this register is used to mask out specific bits when monitoring the bit pattern present at port 0 for interrupt generation. in normal operation where the advanced digital interrupt feature is not being used, any bit which is masked by writing a 1 to that bit will not change state, regardless of the digital data written to port 0. for example, if you set the state of bit 0 low and then mask this bit, the state will remain low, regardless of what you output at port 0 (an output of 1 will not change the bits state until the bit is un- masked). compare register (ba + 30, bits 1 and 0 = 11): this register is used for the advanced digital interrupt modes. in the match mode where an interrupt is generated when the port 0 bits match a loaded value, this register is used to load the bit pattern to be matched at port 0. bits can be selectively masked so that they are ignored when making a match. note: make sure that bit 3 at ba + 30 is set to 1, selecting match mode, before writing the compare register value at this address. in the event mode where an interrupt is generated when any port 0 bit changes its current state, the value which caused the interrupt is latched at this register and can be read from it. bits can be selectively masked using the mask register so a change of state is ignored on these lines in the event mode. www.datasheet.co.kr datasheet pdf - http://www..net/
4-16 ba + 30: read digital irq status/program digital mode (read/write) 8-bit operation. digital irq/strobe status (read): a read shows you whether a digital interrupt has occurred (bit 6), whether a strobe has occurred (bit 7, when using the strobe input as described in chapter 7), and lets you review the states of bits 0 through 5 in this register. if bit 6 is high, then a digital interrupt has taken place. if bit 7 is high, a strobe has been issued. d7 d6 d5 d4 d3 d2 d1 d0 ba + 28 port 0 register select port 1 direction digital irq mode digital irq status 0 = no digital interrupt 1 = digital interrupt digital sample clock select digital irq enable digital mode register (write): port 1 direction 0 = input 1 = output digital irq mode 0 = event mode 1 = match mode d7 d6 d5 d4 d3 d2 d1 d0 ba + 28 port 0 register select 00 = clear mode 01 = direction register 10 = mask register 11 = compare register reserved digital sample clock select 0 = 8 mhz system clock 1 = programmable clock digital irq enable 0 = disabled 1 = enabled bits 0 and 1 C select the clear mode initiated by a read/write operation at ba + 28 or the port 0 control register you talk to at ba + 28 (direction, mask, or compare register). bit 2 C sets the direction of the port 1 digital lines. bit 3 C selects the digital interrupt mode: event (any port 0 bit changes state) or match (port 0 lines match the value programmed into the compare register at ba + 28). bit 4 C disables/enables digital interrupts. bit 5 C sets the clock rate at which the digital lines are sampled when in a digital interrupt mode. available clock sources are the 8 mhz system clock and the output of user tc counter 1 (16-bit programmable clock). when a digital input line changes state, it must stay at the new state for two edges of the clock pulse (62.5 nanoseconds when using the 8 mhz clock) before it is recognized and before an interrupt can be generated. this feature eliminates noise glitches that can cause a false state change on an input line and generate an unwanted interrupt. this feature is detailed in chapter 7. bit 6 C read only (digital irq status). bit 7 C reserved. strobe status 0 = no strobe 1 = strobe www.datasheet.co.kr datasheet pdf - http://www..net/
4-17 programming the 3500 this section gives you some general information about programming and the 3500 board. the 3500 is programmed by writing to and reading from the correct i/o port locations on the board. these i/ o ports were defined in the previous section. because the 3500 is at bus compatible, most operations are done in a 16-bit word format. the 8254 timer/counters must be programmed in 8-bit operations. high-level languages such as pascal, c, and c++ make it very easy to read/write these ports. the table below shows you how to read from and write to i/o ports in turbo c and turbo pascal. in addition to being able to read/write the i/o ports on the 3500, you must be able to perform a variety of operations that you might not normally use in your programming. the table below shows you some of the operators discussed in this section, with an example of how each is used with pascal and c. many compilers have functions that can read/write either 8 or 16 bits from/to an i/o port. for example, turbo pascal uses port for 8-bit port operations and portw for 16 bits, turbo c uses inportb for an 8-bit read of a port and inport for a 16-bit read. be sure to use the correct function for 8- and 16-bit operations with the 3500! clearing and setting bits in a port when you clear or set one or more bits in a port, you must be careful that you do not change the status of the other bits. you can preserve the status of all bits you do not wish to change by proper use of the and and or binary operators. using and and or, single or multiple bits can be easily cleared in one operation. to clear a single bit in a port, and the current value of the port with the value b, where b = 255 - 2 bit . example: clear bit 5 in a port. read in the current value of the port, and it with 223 (223 = 255 - 2 5 ), and then write the resulting value to the port. in basic, this is programmed as: v = inp(portaddress) v = v and 223 out portaddress, v to set a single bit in a port, or the current value of the port with the value b, where b = 2 bit . example: set bit 3 in a port. read in the current value of the port, or it with 8 (8 = 2 3 ), and then write the resulting value to the port. in pascal, this is programmed as: v := port[portaddress]; v := v or 8; port[portaddress] := v; language modulus integer division and or c % a = b % c / a = b / c & a = b & c | a = b | c pascal mod a := b mod c div a := b div c and a := b and c or a := b or c language read 8 bits write 8 bits read 16 bits write16 bits turbo c data=inportb(address) outportb(address,data) data=inport(address) outport(address,data) turbo pascal data:=port[address] port[address]:=data data:=portw[address] portw[address]:=data www.datasheet.co.kr datasheet pdf - http://www..net/
4-18 setting or clearing more than one bit at a time is accomplished just as easily. to clear multiple bits in a port, and the current value of the port with the value b, where b = 255 - (the sum of the values of the bits to be cleared). note that the bits do not have to be consecutive. example: clear bits 2 , 4, and 6 in a port. read in the current value of the port, and it with 171 (171 = 255 - 2 2 - 2 4 - 2 6 ), and then write the resulting value to the port. in c, this is pro- grammed as: v = inportb(port_address); v = v & 171; outportb(port_address, v); to set multiple bits in a port, or the current value of the port with the value b, where b = the sum of the individual bits to be set. note that the bits to be set do not have to be consecutive. example: set bits 3, 5, and 7 in a port. read in the current value of the port, or it with 168 (168 = 2 3 + 2 5 + 2 7 ), and then write the resulting value back to the port. in assembly language, this is programmed as: mov dx, portaddress in al, dx or al, 168 out dx, al often, assigning a range of bits is a mixture of setting and clearing operations. you can set or clear each bit individually or use a faster method of first clearing all the bits in the range then setting only those bits that must be set using the method shown above for setting multiple bits in a port. the following example shows how this two- step operation is done. example: assign bits 3, 4, and 5 in a port to 101 (bits 3 and 5 set, bit 4 cleared). first, read in the port and clear bits 3, 4, and 5 by anding them with 199. then set bits 3 and 5 by oring them with 40, and finally write the resulting value back to the port. in c, this is programmed as: v = inportb(port_address); v = v & 199; v = v | 40; outportb(port_address, v); a final note: dont be intimidated by the binary operators and and or and try to use operators for which you have a better intuition. for instance, if you are tempted to use addition and subtraction to set and clear bits in place of the methods shown above, dont! addition and subtraction may seem logical, but they will not work if you try to clear a bit that is already clear or set a bit that is already set. for example, you might think that to set bit 5 of a port, you simply need to read in the port, add 32 (2 5 ) to that value, and then write the resulting value back to the port. this works fine if bit 5 is not already set. but, what happens when bit 5 is already set? bits 0 to 4 will be unaffected and we cant say for sure what happens to bits 6 and 7, but we can say for sure that bit 5 ends up cleared instead of being set. a similar problem happens when you use subtraction to clear a bit in place of the method shown above. www.datasheet.co.kr datasheet pdf - http://www..net/
5-1 chapter 5 a/d conversions this chapter shows you how to program your 3500 to perform a/d conversions and read the results. included in this discussion are instructions on setting up the channel-gain scan memory, the on-board clocks and sample counter, and various conversion and triggering modes. www.datasheet.co.kr datasheet pdf - http://www..net/
5-2 www.datasheet.co.kr datasheet pdf - http://www..net/
5-3 the following paragraphs walk you through the programming steps for performing a/d conversions. detailed information about the conversion modes and triggering is presented in this section. you can follow these steps in the example programs included with the board. in this discussion, ba refers to the base address. all values are in decimal unless otherwise specified. before starting conversions: initializing the board regardless of the conversion mode you wish to set up, you should always start your program with a board initialization sequence. this sequence should include: clear board command. clear a/d dma done command clear d/a dma done command clear irq command clear dac fifo command clear channel gain table command. clear digital i/o chip. clear a/d fifo command. this initialization procedure clears all board registers, resets the dma done flags to a "0", empties the channel gain table, resets the digital i/o chip and empties the a/d and d/a fifos. all of these commands are carried out by writing and reading from the registers at ba + 0, ba + 28 and ba + 30. since you cannot read back the contents of the control register (ba + 2), trigger register (ba + 6), irq register (ba + 8) or the dac configuration register (ba + 10) we recommend that you store these values in a software variable for each register. these variables should be reset to "0" any time you issue the reset board command. before starting conversions: programming channel, gain and input type the conversion channel, gain and input type are programmed at ba + 4. to program a channel for direct a/d conversion (not using the channel-gain table), you must first point ba + 4 to write to the channel/gain latch. this is done by setting bits d0 and d1 to "00" in the control register at ba + 2. to program the channel, gain and input type, assign the appropriate values to bits 0 through 9 and write this value to ba + 4. the diagram below shows this register. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 000000 00 analog input channel select 0000 = channel 1 0001 = channel 2 0010 = channel 3 0011 = channel 4 0100 = channel 5 0101 = channel 6 0110 = channel 7 0111 = channel 8 1000 = channel 9 1001 = channel 10 1010 = channel 11 1011 = channel 12 1100 = channel 13 1101 = channel 14 1110 = channel 15 1111 = channel 16 gain select 000 = x 1 001 = x 2 010 = x 4 011 = x 8 100 = x 16 101 = x 32 110 = x 64 111 = x 128 a/d se/diff 0 = single-ended 1 = differential www.datasheet.co.kr datasheet pdf - http://www..net/
5-4 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0000 00 the program sequence for programming the channel and gain not using the channel-gain scan memory is: 1. set bits 1 and 0 at ba + 2 to 00 (this points ba + 4 to the channel/gain latch). 2. write the channel and gain data to be loaded to ba + 4. before starting conversions: programming the channel-gain table the channel-gain scan memory can be programmed with 1024 24-bit entries in tabular format. sixteen bits contain the a/d channel-gain data, and 8 bits contain digital control data to support complex channel-gain sequences. to load a new channel-gain table, first clear the channel gain table by writing and reading at ba + 0. to add entries to an existing table, simply write to the a/d table (and digital table if used) as described in the following paragraphs. note that writing beyond the end of the table is ignored. 16-bit a/d table the a/d portion of the channel-gain table with the channel, gain, input type, pause and skip bit information is programmed into the channel-gain scan memory using the a/d table register at ba + 4. this register is defined below. to load channel and gain data into the a/d table, first set bits 1 and 0 at ba + 2 to 01. this points ba + 4 to write to the a/d table. now you can write the 16-bit channel/gain word to ba + 4. if you have cleared the existing table, the first word written will be placed in the first entry of the table, the second word will be placed in the second entry, and so on. if you are adding to an existing table, the new data written will be added at the end. analog input channel select 0000 = channel 1 0001 = channel 2 0010 = channel 3 0011 = channel 4 0100 = channel 5 0101 = channel 6 0110 = channel 7 0111 = channel 8 1000 = channel 9 1001 = channel 10 1010 = channel 11 1011 = channel 12 1100 = channel 13 1101 = channel 14 1110 = channel 15 1111 = channel 16 gain select 000 = x 1 001 = x 2 010 = x 4 011 = x 8 100 = x 16 101 = x 32 110 = x 64 111 = x 128 a/d se/diff 0 = single-ended 1 = differential pause bit 0 = disabled 1 = enabled skip bit 0 = disabled 1 = enabled channel select, gain select and input type the channel number, gain value and input type are entered in the table using bits 0 through 9. each of these parameters can be set independently for every entry in the table. this allows you to set up a complex array of sampling sequences mixing channels, gains and input types. care must be taken in selecting the proper input type. the board is capable of 16 single-ended inputs or 8 differential inputs. you can select combinations of single- ended and differential but each differential channel actually uses 2 single-ended channels. if you select channel 1 to be a differential channel, you must connect your signal to ain1+ (p3-1) and ain1- (p3-2). channel 8 now is not available as a single-ended channel. www.datasheet.co.kr datasheet pdf - http://www..net/
5-5 pause bit bit 10 is used as a pause bit. if this bit is set to a "1"and the pause function is enabled at ba + 2, bit 8, the a/ d conversions will stop at this entry in the table and resume on the next start trigger. this is useful if you have 2 different sequences loaded in the table. you can enable and disable this bit's function at ba + 2, bit 8. note: this bit is ignored in the burst sampling modes. skip bit if bit 11 of the data loaded is set to 1, then the skip bit is enabled and this entry in the channel-gain table will be skipped, meaning an a/d conversion will be performed but the data is not written into the fifo. this feature provides an easy way to sample multiple channels at different rates without saving unwanted data. a simple example illustrates this bits function. in this example, we want to sample channel 1 once each second and channel 4 once every three seconds. first, we must program 6 entries into the channel-gain table. the channel 4 entries with the skip bit set will be skipped when a/d conversions are performed. the table will continue to cycle until a stop trigger is received. next, we will set the pacer clock to run at 2 hz (0.5 seconds). this allows us to sample each channel once per second, the maximum sampling rate required by one of the channels (pacer clock rate = number of different channels sampled x fastest sample rate). the first clock pulse starts an a/d conversion according to the param- eters set in the first entry of the channel-gain table, and each successive clock pulse incrementally steps through the table entries. as shown in figure 5-1 and figure 5-2, the first clock pulse starts a sample on channel 1. the next pulse looks at the second entry in the channel-gain table and sees that the skip bit is set to 1. no a/d data is stored. the third pulse starts a sample on channel 1 again, the fourth pulse skips the next entry, and the fifth pulse takes our third reading on channel 1. on the sixth pulse, the skip bit is disabled and channel 4 is sampled. then the sequence starts over again. samples are not stored when they are not wanted, saving memory and eliminating the need to throw away unwanted data. fig. 5-2 timing diagram for sampling channels 1 and 4 1sec pacer clock a/d conversion channelsampled11141114 fig. 5-1 setting the skip bit 1 4skip 1 4skip 1 4 1 4skip 1 4skip 1 4 1sec 1sec 1sec 1sec 3sec www.datasheet.co.kr datasheet pdf - http://www..net/
5-6 8-bit digital table the digital portion of the channel-gain table can be programmed with digital control information using the digital table register at ba + 4. to load digital control data into the digital table, first set bits 1 and 0 at ba + 2 to 10. this points ba + 4 to write to the digital table. now you can write the 8-bit byte to ba + 4. if you have cleared the existing table, the first byte written will be placed in the first entry of the table, the second byte will be placed in the second entry, and so on. if you are adding to an existing table, the new data written will be added at the end. the first entry made into the digital table lines up with the first entry made into the a/d table, the second entry made into the digital table lines up with the second entry made into the a/d table, and so on. make sure that, if you add to an existing table and did not program the digital table portion when you made your a/d table entries previously, you fill those entries with digital data first before entering the desired added data. since the first digital entry you make always lines up with the first a/d entry made, failure to do this will cause the a/d and digital control data to be misaligned in the table. you cannot turn the digital control lines off for part of a conversion sequence and then turn them on for the remainder of the sequence. note that the digital data programmed here is sent out on the port 1 digital i/o lines whenever this portion of the table is enabled. these lines can be used to control input expansion boards such as the tmx32 analog input expansion board at the same speed as the a/d conversions are performed with no software overhead. note: if you only need to use the a/d part of the table, you do not have to program the digital table. however if you only want to use the digital part of the table you must program the a/d part of the table. setting up a/d and digital tables lets look at how the channel-gain table is set up for a simple example using both the a/d and digital tables. in this example, we have a tmx32 expansion board connected to channel 1 on the 3500. with ba + 2, bits 1 and 0 set to 01, load the channel-gain sequence into the a/d table: entry 1 0000 0000 0000 0000 gain = 1, 3500 channel = 1 entry 2 0000 0000 0010 0000 gain = 4, 3500 channel = 1 entry 3 0000 1000 0000 0000 skip sample entry 4 0000 0000 0010 0000 gain = 4, 3500 channel = 1 entry 5 0000 0000 0000 0000 gain = 1, 3500 channel = 1 entry 6 0000 0000 0010 0000 gain = 4, 3500 channel = 1 with ba + 0, bits 1 and 0 set to 10, load the digital data into the digital table. the first digital word loaded lines up with the first a/d table entry, and so on: entry 1 0000 0000 0000 0000 gain = 1, 3500 channel = 1 0000 0000 tmx32 channel = 1 entry 2 0000 0000 0010 0000 gain = 4, 3500 channel = 1 0000 0011 tmx32 channel = 4 entry 3 0000 1000 0000 0000 skip sample 0000 0000 tmx32 channel = 1 (skip) entry 4 0000 0000 0010 0000 gain = 4, 3500 channel = 1 0000 0011 tmx32 channel = 4 entry 5 0000 0000 0000 0000 gain = 1, 3500 channel = 1 0000 0000 tmx32 channel = 1 entry 6 0000 0000 0010 0000 gain = 4, 3500 channel = 1 0000 0011 tmx32 channel = 4 d7 d6 d5 d4 d3 d2 d1 d0 digital table (set for tmx32): tmx32 channel select 00000 = channel 1 00001 = channel 2 ? 11111 = channel 32 www.datasheet.co.kr datasheet pdf - http://www..net/
5-7 using the channel-gain table for a/d conversions after the channel-gain table is programmed, it must be enabled in order to be used for a/d conversions. two bits control this operation. ba + 2, bit 2 enables the a/d table where the channel and gain data are stored. ba + 2, bit 3 enables the digital table when the digital control data is stored. whenever you want to use the channel-gain table, you must set bit 2 at ba + 2 high to enable the a/d table. if you are also using the digital table, you must enable this portion of the channel-gain table by setting ba + 2, bit 3 high. you cannot use the digital portion without enabling the a/d portion of the channel-gain table (bit 3 cannot be set high unless bit 2 is also high). when the digital table is enabled, the 8-bit data is sent out on the port 1 digital i/o lines. when you are using the channel-gain table to take samples, it is strongly recommended that you do not enable, disable, and then re-enable the table while performing a sequence of conversions. this causes skipping of an entry in the table. in this case you should issue a reset table command at ba + 0. channel-gain table and throughput rates when using the channel-gain table, you should group your entries to maximize the throughput of your module. low-level input signals and varying gains are likely to drop the throughput rate because low level inputs must drive out high level input residual signals. to maximize throughput: ? keep channels configured for a certain range grouped together, even if they are out of sequence. ? use external signal conditioning if you are performing high speed scanning of low level signals. this increases throughput and reduces noise. ? if you have room in the channel-gain table, you can make an entry twice to make sure that sufficient settling time has been allowed and an accurate reading has been taken. set the skip bit for the first entry so that it is ignored. ? for best results, do not use the channel-gain table when measuring steady-state signals. use the single convert mode to step through the channels. channel-gain data store enable (ba + 2, bit 4) when this bit is set to 1, a 16-bit channel-gain table entry is stored in the sample buffer with the converted data. this feature tags each 16-bit conversion with its channel-gain identifier. each channel-gain tag is stored in a 16-bit word in the sample buffer. for each conversion, the tag is sent to the sample buffer, followed by the converted data. when the channel-gain store feature is enabled, the sample buffers capacity is reduced to 512 samples. the channel-gain table data stored in the sample buffer is read as explained later in this chapter. a/d conversion modes to support a wide range of sampling requirements, the 3500 provides several conversion modes with a selection of trigger sources to start and stop a sequence of conversions. understanding how these modes and sources can be configured to work together is the key to understanding the a/d conversion capabilities of your module. the commands issued to the trigger registers at ba + 6 set up how the a/d conversions are controlled. the following paragraphs describe the conversion and trigger modes, and figure 5-3 shows a block diagram of the a/ d conversion select circuitry. start a/d conversions. bits 0, 1 and 2 of the trigger register programmed at ba + 6 control what method is used to actually perform the a/d conversions. one of four modes can be selected: ? through software (by reading ba + 6 to initiate a start convert) ? using a pacer clock (internal (clock tc counter 0 or 1) or external (p3-41)) ? using the burst clock (clock tc counter 2) ? using a digital interrupt generated by the advanced digital interrupt circuit www.datasheet.co.kr datasheet pdf - http://www..net/
5-8 fig. 5-3 a/d conversion select circuitry software trigger (ba+6:read) trigger repeat: enable input output pause enable: input enable output a/d conversion select: software trigger pacer clock burst clock digital interrupt burst trigger select: software trigger pacer clock external trigger digital interrupt pacer clock select: internal external digital interrupt user tc counter 2 out start trigger select (ba+6:d3-d6) trigger repeat enable (ba+6:d15) internal pclk external pclk (p3-41) pclk select (ba+6:d14) pause enable (ba+2:d8) pause bit from channel gain table stop trigger select (ba+6:d7-d10) a/d sample counter stop enable (ba+2:d7) conversion select (ba+6:d0,d2) burst trigger select (ba+6:d11,d13) pacer clock control: enable pause disable gate mode normal mode about trigger mode trigger arm control: arm disarm sample counter stop enable gate: enable output input sample counter: enable output input burst clock: external trigger (p3-39) trigger polarity (ba+2:d11) trigger polarity: start trigger select: software trigger external trigger digital interrupt user tc counter 2 out gate mode: external trigger delay trigger: software trigger external trigger digital interrupt delaymodegate: enable delay counter: enable output input gate mode normal mode software trigger mode delay mode stop trigger select: software trigger external trigger digital interrupt sample counter about trigger: software trigger external trigger digital interrupt user tc counter 2 out user tc counter 2 out www.datasheet.co.kr datasheet pdf - http://www..net/
5-9 start/stop trigger select. the start trigger set at bits 3 through 6 and the stop trigger set at bits 7 through 10 of the trigger register programmed at ba + 6 are used to turn the pacer clock (internal or external) on and off. through these different combinations of start and stop triggers, the 3500 supports pre-trigger, post-trigger, and about-trigger modes with various trigger sources. the start trigger sources are: ? software trigger. when selected, a read at ba + 6 will start the pacer clock. ? external trigger. when selected, a positive- or negative-going edge (depending on the setting of the trigger polarity, bit 11 in the control register) on the external trigger in line, p3-39, will start the pacer clock. the pulse duration should be at least 100 nanoseconds. ? digital interrupt. when selected, a digital interrupt will start the pacer clock. ? user tc counter 2 output. when selected, a pulse on the counter 2 output line (counter 2s count reaches 0) will start the pacer clock. the following start trigger sources provide delayed triggering. when the trigger is issued, the a/d delay counter, counter1 tc, counter 1, counts down and conversions are started when the a/d delay counter reaches 0. the a/d delay counter counts at the pacer clock rate. ? delayed software trigger. when selected, a read at ba + 6 will start the delay counter. ? delayed external trigger. when selected, a positive- or negative-going edge (depending on the setting of the trigger polarity, bit 11 in the control register) on the external trigger in line, p3-39, will start the delay counter. the pulse duration should be at least 100 nanoseconds. ? delayed digital interrupt. when selected, a digital interrupt will start the delay counter. ? delayed user tc counter 2 output. when selected, a pulse on the counter 2 output line (counter 2s count reaches 0) will start the delay counter. ? gate mode. when selected, the pacer clock runs when the external trigger in line, p3-39, is held high. when this line goes low, conversions stop. this trigger mode does not use a stop trigger. if the trigger polarity bit is set for negative, the pacer clock runs when this line is low and stops when it is taken high. the stop trigger sources are: ? software trigger. when selected, a read at ba + 6 will stop the pacer clock. ? external trigger. when selected, a positive- or negative-going edge (depending on the setting of the trigger polarity, bit 11 in the control register) on the external trigger in line, p3-39, will stop the pacer clock. the pulse duration should be at least 100 nanoseconds. ? digital interrupt. when selected, a digital interrupt will stop the pacer clock. ? sample counter. when selected, the pacer clock stops when the sample counters count reaches 0. the next stop trigger sources provide about triggering, where data is acquired from the time the start trigger is received, and continues for a specified number of samples after the stop trigger. the number of samples to acquire after the stop trigger is programmed in the sample counter. ? about software trigger. when selected, a software trigger starts the sample counter, and sampling continues until the sample counters count reaches 0. ? about external trigger. when selected, an external trigger starts the sample counter, and sampling continues until the sample counters count reaches 0. ? about digital interrupt. when selected, a digital interrupt starts the sample counter, and sampling continues until the sample counters count reaches 0. ? about user tc counter 2 output. when selected, a pulse on the counter 2 output line (counter 2s count reaches 0) starts the sample counter, and sampling continues until the sample counters count reaches 0. note that the external trigger (trigger in) can be set to occur on a positive-going edge or a negative-going edge, depending on the setting of bit 11 in the control register at ba + 6. triggering a burst sample. these triggers, set at trigger register bits 11, 12 and 13, ba + 6, can trigger bursts: ? through software (by reading ba + 6 to initiate a start convert) ? using a pacer clock (internal (clock tc counter 0 or 1) or external (p3-41)) www.datasheet.co.kr datasheet pdf - http://www..net/
5-10 ? using an external trigger (p3-39) ? using the digital interrupt trigger repeat function. bit 15 in the trigger register at ba + 6 lets you control the conversion sequence when using a trigger to start the pacer clock. when this bit is low, the first pulse on the trigger line will start the pacer clock. after the stop trigger has ended the conversion cycle, the triggering circuit is disarmed and must be rearmed before another start trigger can be recognized. to rearm this trigger circuit, you must issue a software start convert (read ba + 6). when bit 15 in the trigger register, ba + 6, is high, the conversion sequence is repeated each time an external trigger is received. figure 5-4 shows a timing diagram for this feature. pacer clock source. the pacer clock can be generated from an internal source (clock tc counter 0 or 1) or an external source (p3-41) by setting bit 14 in the trigger register at ba + 6 as desired. types of conversions single conversion. in this mode, a single specified channel is sampled whenever the start convert line is taken high by a read at ba + 6 (software trigger). the active channel is the one specified in the channel/gain register, bits 0 through 6. this is the easiest of all conversions. it can be used in a wide variety of applications, such as sample every time a key is pressed on the keyboard, sample with each iteration of a loop, or watch the system clock and sample every five seconds. figure 5-5 shows a timing diagram for single conversions. multiple conversions. in this mode, conversions are continuously performed at the pacer clock rate. the pacer clock can be internal or external. the maximum rate supported by the board is 100 khz. the pacer clock can be turned on and off using any of the start and stop triggering modes set up in the trigger register at ba + 6. if you use the internal pacer clock, you must program it to run at the desired rate. this mode is ideal for filling arrays, acquiring data for a specified period of time, and taking a specified number of samples. figure 5-6 shows a timing diagram for multiple conversions. external trigger single cycle repeat cycle fig. 5-4 external trigger single cycle vs. repeat cycle 1 1 1 . . . trigger sampled channel sample taken fig. 5-5 timing diagram, single conversion www.datasheet.co.kr datasheet pdf - http://www..net/
5-11 random channel scan. in this mode, the channel-gain table is incrementally scanned through, with each pacer clock pulse starting a conversion at the channel and gain specified in the current table entry. before starting a conversion sequence using the channel-gain table, you need to load the table with the desired data. then make sure that the channel-gain table is enabled by setting bit 2 at ba + 2 high. this enables the a/d portion of the channel-gain table. if you are using the digital table as well, you must also set bit 3 at ba + 2 high. each clock pulse starts a conversion using the current channel-gain data and then increments to the next position in the table. when the last entry is reached, the next pulse starts the table over again. figure 5-7 shows a timing diagram for random channel scanning. programmable burst. in this mode, a single trigger initiates a scan of the entire channel-gain table. before starting a burst of the channel-gain table, you need to load the table with the desired data. then make sure that the channel-gain table is enabled by setting bit 2 at ba + 2 high. this enables the a/d portion of the channel-gain table. if you are using the digital table as well, you must also set bit 3 at ba + 2 high. burst is used when you want one sample from a specified number of channels for each trigger. figure 5-8 shows a timing diagram for burst sampling. as shown, the burst trigger, which is a trigger or pacer clock, triggers the burst and the burst clock initiates each conversion. at high speeds, the burst mode emulates simultaneous sampling of multiple input channels. for time critical simultaneous sampling applications, a simultaneous sample- and-hold board can be used (ss8 eight-channel boards are available from real time devices). 1 1 1 1 1 1 . . . trigger sample taken sampled channel pacer clock 11 1 fig. 5-6 timing diagram, multiple conversions 1 2 3 4 5 9 . . . trigger sample taken channel-gain table entry pacer clock 67 8 fig. 5-7 timing diagram, random channel scan 12 3 trigger sample taken channel-gain table entry burst clock 12 3 burst trigger fig. 5-8 timing diagram, programmable burst www.datasheet.co.kr datasheet pdf - http://www..net/
5-12 programmable multiscan. this mode lets you scan the channel-gain table a specified number of times for each trigger. the total number of samples to be taken is programmed into the sample counter. for example, if you want to take two bursts of a three-entry channel-gain table, as shown in the timing diagram of figure 5-9 below, you would program the sample counter to take six samples. note that if you do not program the sample counter with a multiple of the number of entries in the channel-gain table, the sample counters count will not be 0 when the last burst sequence has been completed, which means that the sample counter will not start at the beginning of the countdown the next time you use it unless it has been reprogrammed. as you can see, the 3500 is designed to support a wide range of conversion requirements. you can set the clocks, triggers, and channel and gain to a number of configurations to perform simple or very complex acquisi- tion schemes where multiple bursts are taken at timed intervals. remember that the key to configuring the board for your application is to understand what signals can actually control conversions and what signals serve as triggers. the diagrams and discussions presented in this section and the example programs on the disk should help you to understand how to configure the board. starting an a/d conversion depending on your conversion and trigger settings, the software trigger command (read at ba + 6) has different functions. in any mode that uses the software trigger, this command will do the appropriate action. for example, if you set the start trigger as software trigger, the read at ba + 6 will start the pacer clock running. however, in any mode that does not use the software trigger as the trigger, you will still need to do a read at ba + 6 to arm (enable) the triggering circuitry. an example of this would be, if you set the start trigger as external trigger, a read at ba + 6 is required to arm the external trigger circuitry. after you have set all the trigger and conversion registers to the proper values, the last command will need to be a software trigger. any external triggers received before this command will be ignored. it is also a good practice to clear the a/d fifo just prior to triggering the measurement or arming the trigger. study the example programs to see this sequence. monitoring conversion status the a/d conversion status can be monitored through the a/d fifo empty flag in the status word read at ba + 2. typically, you will want to monitor the ef flag for a transition from low to high. this tells you that a conversion is complete and data has been placed in the sample buffer. halting conversions in single convert modes, a single conversion is performed and the module waits for another start convert command. in multi-convert modes, conversions are halted by one of two methods: when a stop trigger has been issued to stop the pacer clock, or when the fifo is full. the halt flag, bit 1 of the status word (ba + 2), is set when the sample buffer is full, disabling the a/d converter. even if youve removed data from the sample buffer since the buffer filled up and the fifo full flag is no longer set, the halt bit will confirm that at some point in your 12 3 sample taken channel-gain table entry pacer clock 12 3 trigger sample counter output 12 3 1 2 3 fig. 5-9 timing diagram, programmable multiscan www.datasheet.co.kr datasheet pdf - http://www..net/
5-13 conversion sequence, the sample buffer filled and conversions were halted. at this point a clear fifo command must be issued and a software start convert (read at ba + 6) to rearm the trigger circuitry. reading the converted data each 16-bit conversion is stored in a 16-bit word in the sample buffer. the buffer can store 1024 samples. if you want to tag each conversion with its channel-gain table identifier, the channel-gain tag is stored in a 16-bit word in the sample buffer. this section explains how to read the data stored in the sample buffer. reading data with the channel-gain data store bit disabled when the channel-gain data store bit is disabled, the sample buffer contains only the converted data in a 16- bit word. the output code format is two's complement. the data should always be read from the a/d fifo as a signed integer. voltage values for each bit will vary depending on gain. for example, if the input is set for gain = 1, the formula for calculating voltage is as follows: voltage = ((input range / gain) / 65536) x conversion data voltage = ((20 / 1) / 65536) x conversion data voltage = 305.18 uv x conversion data remember that when you change the gain, you are increasing the resolution of the bit value but you are decreasing the input range. in the above example if we change the gain to 4, each bit will now be equal to 76.3 uv but our input range is decreased from 20 volts to 5 volts. the formula would look like this: voltage = ((input range / gain) / 65536) x conversion data voltage = ((20 / 4) / 65536) x conversion data voltage = 76.3 uv x conversion data the key digital codes and their input voltage values are given in the following tables. the bit map below shows the configuration of the a/d data. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 bit 16 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) (msb) www.datasheet.co.kr datasheet pdf - http://www..net/
5-14 reading data with the channel-gain data store bit enabled when the channel-gain data store bit is enabled, the sample buffer contains two 16-bit words for each 16-bit conversion: the 16-bit channel-gain data word followed by the 16-bit converted data word. figure 5-10 shows how these words are sent to the sample buffer. below is the format of the 16-bit channel-gain data word. fifo 16-bit a/d converted data bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 select bit 15 bit 0 bit 15 bit 8 bit 7 bit 0 from a/d converter from channel/ gain table channel/ gain data digital control data fig. 5-10 sample buffer circuitry a/d converter bit weights, bipolar, twos complement a/d bit weight ideal input voltage (millivolts) a/d bit weight ideal input voltage (millivolts) 1111 1111 1111 1111 -0.305176 0000 0000 1000 0000 +39.062500 1000 0000 0000 0000 -10000.000000 0000 0000 0100 0000 +19.531250 0100 0000 0000 0000 +5000.000000 0000 0000 0010 0000 +9.775625 0010 0000 0000 0000 +2500.000000 0000 0000 0001 0000 +4.882813 0001 0000 0000 0000 +1250.000000 0000 0000 0000 1000 +2.441406 0000 1000 0000 0000 +625.000000 0000 0000 0000 0100 +1.220703 0000 0100 0000 0000 +312.500000 0000 0000 0000 0010 +0.610352 0000 0010 0000 0000 +156.250000 0000 0000 0000 0001 +0.305176 0000 0001 0000 0000 +78.125000 0000 0000 0000 0000 0.000000 www.datasheet.co.kr datasheet pdf - http://www..net/
5-15 the bottom 8 bits contain the channel and gain information. the upper 8 bits contain the digital i/o port 1 lines. this information is useful if you are using the digital part of the channel/gain table. if you are not using the digital part of the table, these bits will contain whatever the bit pattern at port 1 is. remember that when you have the channel-gain data store enabled, each sample in the fifo will consist of two 16-bit words. the first word will contain the channel-gain information shown above and the second 16-bit word will contain the a/d data. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 0 analog input channel select 0000 = channel 1 0001 = channel 2 0010 = channel 3 0011 = channel 4 0100 = channel 5 0101 = channel 6 0110 = channel 7 0111 = channel 8 1000 = channel 9 1001 = channel 10 1010 = channel 11 1011 = channel 12 1100 = channel 13 1101 = channel 14 1110 = channel 15 1111 = channel 16 gain select 000 = x 1 001 = x 2 010 = x 4 011 = x 8 100 = x 16 101 = x 32 110 = x 64 111 = x 128 digital i/o port 1 www.datasheet.co.kr datasheet pdf - http://www..net/
5-16 programming the pacer clock two 16-bit timers in the clock tc, counters 0 and 1, are cascaded to form a 16-bit or 32-bit on-board pacer clock, shown in figure 5-11. when you want to use the pacer clock for continuous a/d conversions, you must select a 16-bit or 32-bit clock configuration and program the clock rate. selecting 16-bit or 32-bit pacer clock the size of the pacer clock, 16-bit or 32-bit, is programmed at bit 10 of the control register at ba + 2. when this bit is set to 0, a 16-bit pacer clock is selected. whenever possible, it is strongly recommended that the 16-bit pacer clock be used to minimize the delay between the time a trigger occurs and the first conversion is initiated by the pacer clock. when using a 16-bit clock, the first conversion will always start within 250 nanoseconds of the trigger, and subsequent conversions are synchronized to the pacer clock. the 16-bit clock conversion speeds can be set from 100 khz down to 123 hz. because the 32-bit pacer clock cascades two 16-bit timers, the uncertainty between the time a trigger occurs and the first conversion is initiated can be significantly greater than for the 16-bit clock. the triggering uncer- tainty here is based on the value programmed into the first divider and can become unacceptable for certain applications. however, for conversion rates slower than 123 hz, you must use the 32-bit pacer clock. the 32-bit clock is selected by setting bit 10 in the control register to 1. when programming the 32-bit clock, you should always program the smallest possible value in divider 1 in order to minimize the triggering uncertainty. programming steps the pacer clock is accessed for programming by setting bits 6 and 5 at ba + 2 to 00. to find the value you must load into the clock to produce the desired rate, you first have to calculate the value of divider 1 (clock tc counter 0) for a 16-bit clock, or the value of divider 1 and divider 2 (clock tc counter 1) for a 32-bit clock, as shown in figure 5-12. the formulas for making this calculation are as follows: 16-bit pacer clock frequency = 8 mhz/(divider 1) divider 1 = 8 mhz/16-bit pacer clock frequency 32-bit pacer clock frequency = 8 mhz/(divider 1 x divider 2) divider 1 x divider 2 = 8 mhz/32-bit pacer clock frequency to set the 16-bit pacer clock frequency at 100 khz, this equation becomes: divider 1 = 8 mhz/100 khz ---> 80 = 8 mhz/100 khz when divider 1 is greater than 65,536, you will have to select a 32-bit pacer clock and program the clock rate into dividers 1 and 2. when programming the 32-bit clock, divide the result by the least common denominator. the least common denominator is the value that is loaded into divider 1, and the result of the division, the quotient, is loaded into divider 2. the tables below list some common pacer clock frequencies and the counter settings for a 16-bit and a 32-bit pacer clock. after you calculate the decimal value of each divider, you can convert the result to a hex value if it is easier for you when loading the count into each 16-bit counter. fig. 5-11 pacer clock block diagram 16/32-bit pacer clock select counter 0 divider 1 counter 1 divider 2 8mhz pacer clock www.datasheet.co.kr datasheet pdf - http://www..net/
5-17 to set up the 16-bit pacer clock, follow these steps: 1. set pacer clock size to 16 bits (bit 10 of control register at ba + 2 = 0). 2. set ba + 2, bits 6 and 5 to 00 to talk to the clock tc. 3. program counter 0 for mode 2 operation. 4. load divider 1 lsb. 5. load divider 1 msb. to set up the 32-bit pacer clock, follow these steps: 1. set pacer clock size to 32 bits (bit 10 of control register at ba + 2 = 1). 2. set ba + 2, bits 6 and 5 to 00 to talk to the clock tc. 3. program counter 0 for mode 2 operation. 4. program counter 1 for mode 2 operation. 5. load divider 1 lsb. 6. load divider 1 msb. 7. load divider 2 lsb. 8. load divider 2 msb. depending on your conversion mode, the counters start their countdown and the pacer clock starts running when a trigger occurs. programming the burst clock the third 16-bit timer in the clock tc, counter 2, is the on-board burst clock. when you want to use the burst clock for performing a/d conversions in the burst mode, you must program the clock rate. to find the value you must load into the clock to produce the desired rate, make the following calculation: burst clock frequency = 8 mhz/counter 2 divider to set the burst clock frequency at 100 khz using the on-board 8 mhz clock source, this equation becomes: burst clock frequency = 8 mhz/100 khz ---> 80 = 8 mhz/100 khz after you determine the value that will result in the desired clock frequency, load it into counter 2. in this case, decimal 80 (hex 0050) is loaded into the counter. to set up the burst clock, follow these steps: 1. set ba + 2, bits 6 and 5 to 00 to talk to the clock tc. 2. program counter 2 for mode 2 operation. 3. load divider lsb. 4. load divider msb. 32-bit pacer clock divider 1 decimal / (hex) divider 2 decimal / (hex) 100 hz 2 / (0002) 40000 / (9c40) 10 hz 16 / (0010) 50000 / (c350) 16-bit pacer clock divider 1 decimal / (hex) 100 khz 80 / (0050) 50 khz 160 / (00a0) 10 khz 800 / (0320) 1 khz 8000 / (1f40) www.datasheet.co.kr datasheet pdf - http://www..net/
5-18 depending on your conversion mode, the counter start its countdown and the burst clock starts running when a trigger occurs. programming the sample counter the sample counter lets you program the 3500 to take a certain number of samples and then halt conversions. the number of samples to be taken is loaded into the 16-bit sample counter, counter1 tc counter 0. recall that because of the operating structure of the 8254, the count loaded initially is not the count which is counted down during the first cycle. a software correction is used as an easy means to compensate for this. two pulses of the counter are required to actually load the desired count and prepare the counter to count down correctly (this can be looked at as the initialization procedure for the sample counter). a pulse is sent to the 8254 sample counter each time you read ba + 14. without this correction, the initial count sequence will be off by two pulses. note that once the counter is properly loaded and starts, any subsequent countdowns of this count will be accurate. after you determine the desired number of samples, load the count into counter1 tc counter 0. to set up the sample counter, follow these steps: 2. set ba + 2, bits 6 and 5 to 01 to talk to the counter1 tc. 2. program counter 0 for mode 2 operation. 3. load count lsb. 4. load count msb. 5. pulse line by reading ba + 14 two times so that the loaded count matches the desired count. using the sample counter to create large data arrays the 16-bit sample counter allows you to take up to 65,535 samples before the count reaches 0 and sampling is halted. suppose, however, you want to take 100,000 samples and stop. the 3500 provides a bit in the control register at ba + 2 which allows you to use the sample counter to take more than 65,535 samples in a conversion sequence. bit 7 in the control register, the sample counter stop enable bit, can be set to 1 to allow the sample counter to continuously cycle through the loaded count until the stop enable bit is set to 0, which then causes the sample counter to stop at the end of the current cycle. lets look back at our example where we want to take 100,000 readings. first, we must divide 100,000 by a whole number that gives a result of less than 65,535. in our example, we can divide as follows: sample counter count = 100,000 / 2 = 50,000 to use the sample counter to take 100,000 samples, we will load a value of 50,000 into the counter and cycle the counter two times. after the value is loaded, make sure that bit 7 in the control register is set to 1 so that the sample counter will cycle. then, set up the sample counter so that it generates an interrupt when the count reaches 0. initialize the sample counter as described in the preceding section and start the conversion sequence. when the sample counter interrupt occurs telling you that the count has reached 0 and the cycle is starting again, set bit 7 in the control register to 0 to stop the sample counter after the second cycle is completed. the result: the sample counter runs through the count two times and 100,000 samples are taken. figure 5-12 shows a timing diagram for this example. www.datasheet.co.kr datasheet pdf - http://www..net/
5-19 fig. 5-12 timing diagram for cycling the sample counter pacer clock sample counter out (irq) 123 50000 100000 sample counter stop enable trigger www.datasheet.co.kr datasheet pdf - http://www..net/
5-20 www.datasheet.co.kr datasheet pdf - http://www..net/
6-1 chapter 6 data transfers using dma this chapter explains how data transfers are accomplished using dma. www.datasheet.co.kr datasheet pdf - http://www..net/
6-2 www.datasheet.co.kr datasheet pdf - http://www..net/
6-3 direct memory access (dma) transfers data between a peripheral device and pc memory without using the processor as an intermediate. bypassing the processor in this way allows very fast transfer rates. all pcs contain the necessary hardware components for accomplishing dma. however, software support for dma is not included as part of the bios or dos, leaving you with the task of programming the dma controller yourself. with a little care, such programming can be successfully and efficiently achieved. the following discussion is based on using the dma controller to get data from a peripheral device and write it to memory. the opposite can also be done; the dma controller can read data from memory and pass it to a peripheral device. there are a few minor differences, mostly in programming the dma controller, but in general the process is the same. the following steps are required when using dma: 1. choose a dma channel. 2. allocate a buffer. 3. calculate the page and offset of the buffer. 4. set the dma page register. 5. program the 8237 dma controller. 6. program device generating data (3500). 7. enable dma channel. 8. wait until dma is complete. 9. disable dma channel. each step is detailed in the following paragraphs. ? choosing a dma channel there are a number of dma channels available on the pc for use by peripheral devices. the 3500 can use dma channel 5, 6, or 7, selected through software. you can arbitrarily choose any of these; in most cases your choice will be fine. occasionally though, you will have another peripheral device (for example, a tape backup or bernoulli drive) that also uses the dma channel you have selected. this will certainly cause erratic results and can be hard to detect. the best approach to pinpoint this problem is to read the documentation for the other peripheral devices in your system and try to determine which dma channel each uses. ? allocating a dma buffer when using dma, you must have a location in memory where the 8237 dma controller will place the 16-bit data words from the 3500 board. this buffer can be either static or dynamically allocated. the buffer must start on a word boundary (i.e., even numbered address). you should force your compiler to use word alignment for data. be sure that its location will not change while dma is in progress. the following code examples show how to allocate buffers for use with dma. in pascal: var buffer : array[1..10000] of byte; { static allocation } -or- var buffer : ^byte; {dynamic allocation } . . . buffer := getmem(10000); in c: char buffer[10000]; /* static allocation */ -or- char *buffer; /* dynamic allocation */ . . . buffer = calloc(10000, 0); www.datasheet.co.kr datasheet pdf - http://www..net/
6-4 ? calculating the page and offset of a buffer once you have a buffer into which to place your data, you must inform the 8237 dma controller of the location of this buffer. this is a little more complex than it sounds because the dma controller uses a page :offset memory scheme, while you are probably used to thinking about your computers memory in terms of a segment :offset scheme. paged memory is simply memory that occupies contiguous, non-overlapping blocks of memory, with each block being 64k (one page) in length. the first page (page 0) starts at the first byte of memory, the second page (page 1) starts at byte 65536, the third page (page 2) at byte 131072, and so on. a computer with 640k of memory has 10 pages of memory. the dma controller can write to (or read from) only one page without being reprogrammed. this means that the dma controller has access to only 64k of memory at a time. if you program it to use page 3, it cannot use any other page until you reprogram it to do so. when dma is started, the dma controller is programmed to place data at a specified offset into a specified page (for example, start writing at word 512 of page 3). each time a word of data is written by the controller, the offset is automatically incremented so the next word will be placed in the next memory location. the problem for you when programming these values is figuring out what the corresponding page and offset are for your buffer. most compilers contain macros or functions that allow you to directly determine the segment and offset of a data structure, but not the page and offset. therefore, you must calculate the page number and offset yourself. probably the most intuitive way of doing this is to convert the segment:offset address of your buffer to a linear address and then convert that linear address to a page:offset address. the table below shows functions/macros for determining the segment and offset of a buffer. once youve determined the segment and offset, multiply the segment by 16 and add the offset to give you the linear address. (make sure you store this result as a long integer, or dword, or the results will be meaning- less.) the linear address is a 20-bit value, with the upper 4 bits representing the page and the lower 16 bits representing the offset into the page. even though the upper 4 bits are the page, only the upper 3 bits, d17, d18, and d19, are sent to what is called the page register. the remaining bit for the page, d16, is sent to the base address register of the dma controller along with bits d1 through d15. since the buffer sits on a word boundary, bit d0 must be zero, and is ignored. the following diagram shows you to which registers the components of the 20-bit linear address are sent. 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 language segment offset c fp_seg s = fp_seg(&buffer) fp_off o = fp_off(&buffer) pascal seg s := seg(buffer) ofs o := ofs(buffer) to 8237 base address msb to page register to 8237 base address lsb www.datasheet.co.kr datasheet pdf - http://www..net/
6-5 the following examples show you how to calculate the linear address and break it into components to be sent to the various registers. in pascal: segment := seg(buffer); { get segment of buffer } offset := ofs(buffer); { get offset of buffer } linearaddress := segment * 16 + offset; { calculate linear address } pagebits := (linearaddress div 65536) and $0e; { determine page corresponding to this,linear address and clear least significant bit } offsetbits := (linearaddress shr 2) mod 65536; { shift linear address to ignore d0 then extract bits d1-d16 } in c: segment = fp_seg(&buffer); /* get segment of buffer */ offset = fp_ofs(&buffer); /* get offset of buffer */ linear_address = segment * 16 + offset; /* calculate linear address */ pagebits = (linear_address / 65536) & 0x0e; /* determine page corresponding to this linear address and clear least significant bit */ offset_bits = (linear_address >> 2) % 65536; /* shift linear address to ignore d0 then extract bits d1-d16 */ beware! there is one big catch when using page-based addresses. the 8237 dma controller cannot write properly to a buffer that straddles a page boundary. a buffer straddles a page boundary if one part of the buffer resides in one page of memory while another part resides in the following page. the dma controller cannot properly write to such a buffer because the dma controller can only write to one page without reprogramming. when it reaches the end of the current page, it does not start writing to the next page. instead, it starts writing back at the first byte of the current page. this can be disastrous if the beginning of the page does not correspond to your buffer. more often than not, this location is being used by the code portion of your program or the operat- ing system, and writing data to it will almost always causes erratic behavior and an eventual system crash. you must check to see if your buffer straddles a page boundary and, if it does, take action to prevent the dma controller from trying to write to the portion that continues on the next page you can reduce the size of the buffer or try to reposition the buffer. however, this can be difficult when using large static data structures, and often, the only solution is to use dynamically allocated memory. ? setting the dma page register oddly enough, you do not inform the dma controller directly of the page to be used. instead, you put the page to be used into the dma page register, with the least significant bit set to zero. the dma page register is separate from the dma controller, as shown in the table below. dma channel location of page register 5 8b/(139) 6 89/(137) 7 8a/(138) www.datasheet.co.kr datasheet pdf - http://www..net/
6-6 ? the dma controller the dma controller is made up of two complex 8237 chips, one for dma channels 0-3, and one for channels 4-7, that occupy 32 contiguous bytes of the at i/o port space starting with port c0h. a complete discussion of how it operates is beyond the scope of this manual; only relevant information is included here. the dma control- ler is programmed by writing to the dma registers in your at. the table below lists these registers. if you are using dma channel 5, write your page offset bits to port c4h and the count to c6h; for channel 6, write the offset to c8h and the count to cah; for channel 7, write the offset to cch and the count to ceh. the page offset bits are the bits you calculated as shown above. count indicates the number of samples that you want the dma controller to transfer. the value that you write to the dma controller is (number of samples - 1). the mask register and mode register are described below. ? dma mask register the dma mask register is used to enable or disable dma on a specified dma channel. you should mask (disable) dma on the dma channel you will be using while programming the dma controller. after the dma controller has been programmed and the 3500 has been programmed to sample data, you can enable dma by clearing the mask bit for the dma channel you are using. you should manually disable dma by setting the mask bit before exiting your program or, if for some reason, sampling is halted before the dma controller has trans- ferred all the data it was programmed to transfer. if you leave dma enabled and it has not transferred all the data it was programmed to transfer, it will resume transfers the next time data appears at the a/d converter. this can spell disaster if your program has ended and the buffer has been reallocated to another application. dma registers address hex/(decimal) location of page register 8b/(139) channel 5 dma page select c4/(196) channel 5 dma base address c6/(198) channel 5 dma count 89/(137) channel 6 dma page select c8/(200) channel 6 dma base address ca/(202) channel 6 dma count 8a/(138) channel 7 dma page select cc/(204) channel 7 dma base address ce/(206) channel 7 dma count d4/(212) mask register d6/(214) mode register d8/(216) byte pointer flip-flop d7 d6 d5 d4 d3 d2 d1 d0 i/o port d4h channel select 00 = channel 4 01 = channel 5 10 = channel 6 11 = channel 7 mask bit 0 = unmask 1 = mask www.datasheet.co.kr datasheet pdf - http://www..net/
6-7 ? dma mode register the dma mode register is used to set parameters for the dma channel you will be using. the read/write bits are self explanatory; the read used for d/a transfers and write used for a/d transfers. autoinitialization allows the dma controller to automatically start over once it has transferred the requested number of words. decrement means the dma controller should decrement its offset counter after each transfer; the default is increment. we recommend that you use either the demand or single transfer mode when transferring data. block mode transfer is not supported by this board. ? programming the dma controller to program the dma controller, follow these steps: 1. disable dma on the channel you are using. 2. write the dma mode register to choose the dma parameters. 3. write the page offset bits (d1-d16) of your buffer. 4. write the number of samples to transfer. 5. write the page register. 6. enable dma on the channel you are using. ? programming the 3500 for dma once you have set up the dma controller, you must program the 3500 for dma. the following steps list this procedure: 1. program conversion and trigger mode. 2. program the dma channel at ba + 2 (a/d) or ba + 10 (d/a). 3. issue the start trigger. ? monitoring for dma done there are two ways to monitor for dma done. the easiest is to poll the dma done bits in the 3500 status register (ba +2). while dma is in progress, the bit is clear (0). when dma is complete, the bit is set (1). the second way to check is to use the dma done signal to generate an interrupt. an interrupt can immediately notify your program that dma is done and any actions can be taken as needed. ? dual dma mode the 3500 is capable of running in dual dma mode for the a/d. this is useful for acquiring large amounts of data at a high speed. in dual dma mode, you must allocate two dma buffers and program two dma channels as described above. to program the 3500, you must setup the first dma channel at ba + 2, bits 12 and 13 and set up the second dma channel at ba + 2, bits 14 and 15. in this mode, dma will start and use the first channel and buffer you have set up. when the dma done for this channel is received, the board will automatically switch to the second channel and buffer. while the board is filling the second buffer, you can empty the first buffer or reprogram the first channel to point to a different buffer. this allows you to stream large quantities of data to memory with very small amounts of software overhead. offset counter 0 = increment 1 = decrement transfer mode 00 = demand 01 = single transfer 10 = block 11 = cascade d7 d6 d5 d4 d3 d2 d1 d0 i/o port d6h channel select 00 = channel 4 01 = channel 5 10 = channel 6 11 = channel 7 read/write 01 = write (a/d transfers) 10 = read (d/a transfers) autoinitialization 0 = disable 1 = enable www.datasheet.co.kr datasheet pdf - http://www..net/
6-8 ? common dma problems ? make sure that your buffer is large enough to hold all of the data you program the dma controller to transfer. ? check to be sure that your buffer does not straddle a page boundary. ? remember that the value for the number of samples for the dma controller to transfer is equal to (the number of samples - 1). ? if you terminate sampling before the dma controller has transferred the number of bytes it was pro- grammed for, be sure to disable dma by setting the mask bit in the mask register. ? if you are in dual dma mode, be sure to clear the dma done bit after each dma cycle is complete. www.datasheet.co.kr datasheet pdf - http://www..net/
7-1 chapter 7 interrupts this chapter explains software selectable interrupts, digital interrupts, and basic interrupt programming techniques. www.datasheet.co.kr datasheet pdf - http://www..net/
7-2 www.datasheet.co.kr datasheet pdf - http://www..net/
7-3 the 3500 has two completely independent interrupt circuits which can generate interrupts on irq channels 3, 5, 9, 10, 11, 12 or 15. by using these two circuits, complex data acquisition systems can be configured. software selectable interrupt sources each interrupt circuit on the 3500 has 18 software selectable interrupt sources which can be programmed in bits 0 through 4 and bits 8 through 12 of the interrupt register at ba + 8, as described and shown below. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 irq1 source select 00000 = a/d sample counter 00001 = a/d start convert 00010 = a/d fifo half-full 00011 = a/d dma done 00100 = reset channel-gain table 00101 = pause channel-gain table 00110 = external pacer clock 00111 = external trigger 01000 = dac1 sample counter 01001 = dac2 sample counter 01010 = dac1 dma done 01011 = dac2 dma done 01100 = digital interrupt 1 01101 = user tc counter 1 out 01110 = user tc counter 1 out inverted 01111 = user tc counter 2 out 10000 = reserved 10001 = reserved 10010 = reserved 10011 = reserved 10100 = external interrupt 10101 = digital interrupt 2 10110 - 11111 = reserved irq1 channel select 000 = disabled 001 = irq3 010 = irq5 011 = irq9 100 = irq10 101 = irq11 110 = irq12 111 = irq15 irq2 source select 00000 = a/d sample counter 00001 = a/d start convert 00010 = a/d fifo half-full 00011 = a/d dma done 00100 = reset channel-gain table 00101 = pause channel-gain table 00110 = external pacer clock 00111 = external trigger 01000 = dac1 sample counter 01001 = dac2 sample counter 01010 = dac1 dma done 01011 = dac2 dma done 01100 = digital interrupt 1 01101 = user tc counter 1 out 01110 = user tc counter 1 out inverted 01111 = user tc counter 2 out 10000 = reserved 10001 = reserved 10010 = reserved 10011 = reserved 10100 = external interrupt 10101 = digital interrupt 2 10110 - 11111 = reserved irq2 channel select 000 = disabled 001 = irq3 010 = irq5 011 = irq9 100 = irq10 101 = irq11 110 = irq12 111 = irq15 a/d sample counter - an interrupt is generated when the a/d sample counter count reaches 0. a/d start convert - an interrupt is generated when a conversion is started. a/d fifo half full - an interrupt is generated when the a/d fifo is half-full. a/d dma done - an interrupt is generated when the a/d dma done flag goes high. reset channel-gain table - an interrupt is generated when the channel-gain table resets to the beginning. pause channel-gain table - an interrupt is generated when a pause occurs in the channel-gain table. external pacer clock - an interrupt is generated when the external pacer clock line is pulsed. external trigger - an interrupt is generated when the external trigger line is pulsed. dac1 sample counter - an interrupt is generated when the dac1 sample counter reaches 0. dac2 sample counter - an interrupt is generated when the dac2 sample counter reaches 0. dac1 dma done - an interrupt is generated when the dac1 dma done flag goes high. dac2 dma done - an interrupt is generated when the dac2 dma done flag goes high. digital interrupt 1 - an interrupt is generated by the first digital i/o chip. user tc counter 1 out - an interrupt is generated when user tc counter 1s count reaches 0. user tc counter 1 out inverted - an interrupt is generated when user tc counter 1s count reaches 0 (useful for frequency counting). user tc counter 2 out - an interrupt is generated when user tc counter 2s count reaches 0. external interrupt - an interrupt is generated when the external interrupt line is pulsed. digital interrupt 2 - an interrupt is generated by the second digital i/o chip. www.datasheet.co.kr datasheet pdf - http://www..net/
7-4 software selectable interrupt channel each interrupt circuit on the 3500 has 7 software selectable interrupt channels which can be programmed in bits 5 through 7 and bits 13 through 15 of the interrupt register at ba + 8. the interrupt output is driven by an open collector device which is turned off when the irq channel is set to disable. at power up or reset, this register is set to all zero's. advanced digital interrupts the bit programmable digital i/o circuitry supports two advanced digital interrupt modes, event mode or match mode. these modes are used to monitor input lines for state changes. the mode is selected at ba + 30, bit 3 and enabled at ba + 30, bit 4. event mode when enabled, this mode samples the port 0 input lines at a specified clock rate (using the 8 mhz system clock or a programmable clock in user tc counter 1), looking for a change in state in any one of the eight bits. when a change of state occurs, an interrupt is generated and the input pattern is latched into the compare regis- ter. you can read the contents of this register at ba + 28 to see which bit caused the interrupt to occur. bits can be masked and their state changes ignored by programming the mask register with the mask at ba + 28. match mode when enabled, this mode samples the port 0 input lines at a specified clock rate (using the 8 mhz system clock or a programmable clock in user tc counter 1) and compares all input states to the value programmed in the compare register at ba + 28. when the states of all of the lines match the value in the compare register, an interrupt is generated. bits can be masked and their states ignored by programming the mask register with the mask at ba + 28. sampling digital lines for change of state in the advanced digital interrupt modes, the digital lines are sampled at a rate set by the 8 mhz system clock or the clock programmed in user tc counter 1. with each clock pulse, the digital circuitry looks at the state of the next port 0 bits. to provide noise rejection and prevent erroneous interrupt generation because of noise spikes on the digital lines, a change in the state of any bit must be seen for two edges of a clock pulse to be recognized by the circuit. figure 7-1 shows a diagram of this circuit. fig. 7-1 digital interrupt timing diagram digital input clock irq out www.datasheet.co.kr datasheet pdf - http://www..net/
7-5 basic programming for interrupt handling ? what is an interrupt? an interrupt is an event that causes the processor in your computer to temporarily halt its current process and execute another routine. upon completion of the new routine, control is returned to the original routine at the point where its execution was interrupted. interrupts are very handy for dealing with asynchronous events (events that occur at less than regular inter- vals). keyboard activity is a good example; your computer cannot predict when you might press a key and it would be a waste of processor time for it to do nothing while waiting for a keystroke to occur. thus, the interrupt scheme is used and the processor proceeds with other tasks. then, when a keystroke does occur, the keyboard interrupts the processor, and the processor gets the keyboard data, places it in memory, and then returns to what it was doing before it was interrupted. other common devices that use interrupts are modems, disk drives, and mice. your 3500 board can interrupt the processor when a variety of conditions are met, such as dma done, timer countdown finished, end-of-convert, and external trigger. by using these interrupts, you can write software that effectively deals with real world events. ? interrupt request lines to allow different peripheral devices to generate interrupts on the same computer, the at bus has 16 differ- ent interrupt request (irq) lines. a transition from low to high on one of these lines generates an interrupt request which is handled by one of the ats two interrupt control chips. one chip handles irq0 through irq7 and the other chip handles irq8 through irq15. the controller which handles irq8-irq15 is chained to the first controller through the irq2 line. when an irq line is brought high, the interrupt controllers check to see if interrupts are to be acknowledged from that irq and, if another interrupt is already in progress, they decide if the new request should supersede the one in progress or if it has to wait until the one in progress is done. this prioritizing allows an interrupt to be interrupted if the second request has a higher priority. the priority level is determined by the number of the irq. because of the configuration of the two controllers, with one chained to the other through irq2, the priority scheme is a little unusual. irq0 has the highest priority, irq1 is second-highest, then priority jumps to irq8, irq9, irq10, irq11, irq12, irq13, irq14, and irq15, and then following irq15, it jumps back to irq3, irq4, irq5, irq6, and finally, the lowest priority, irq7. this sequence makes sense if you consider that the controller that handles irq8-irq15 is routed through irq2. ? 8259 programmable interrupt controllers the chips responsible for handling interrupt requests in the pc are the 8259 programmable interrupt control- lers. the 8259 that handles irq0-irq7 is referred to as 8259a, and the 8259 that handles irq8-irq15 is referred to as 8259b. to use interrupts, you need to know how to read and set the 8259 interrupt mask registers (imr) and how to send the end-of-interrupt (eoi) command to the 8259s. ? interrupt mask registers (imr) each bit in the interrupt mask register (imr) contains the mask status of an irq line; in 8259a, bit 0 is for irq0, bit 1 is for irq1, and so on, while in 8259b, bit 0 is for irq8, bit 1 is for irq9, and so on. if a bit is set (equal to 1), then the corresponding irq is masked and it will not generate an interrupt. if a bit is clear (equal to 0), then the corresponding irq is unmasked and can generate interrupts. the imr for irq0-irq7 is programmed through port 21h, and the imr for irq8-irq15 is programmed through port a1h. irq7 irq6 irq5 irq4 irq3 irq2 irq1 irq0 irq15 irq14 irq13 irq12 irq11 irq10 irq9 irq8 i/o port 21h i/o port a1h for all bits: 0 = irq unmasked (enabled) 1 = irq masked (disabled) www.datasheet.co.kr datasheet pdf - http://www..net/
7-6 ? end-of-interrupt (eoi) command after an interrupt service routine is complete, the appropriate 8259 interrupt controller must be notified. when using irq0-irq7, this is done by writing the value 20h to i/o port 20h only; when using irq8-irq15, you must write the value 20h to i/o ports 20h and a0h. ? what exactly happens when an interrupt occurs? understanding the sequence of events when an interrupt is triggered is necessary to properly write software interrupt handlers. when an interrupt request line is driven high by a peripheral device (such as the ada3500), the interrupt controllers check to see if interrupts are enabled for that irq, and then checks to see if other inter- rupts are active or requested and determine which interrupt has priority. the interrupt controllers then interrupt the processor. the current code segment (cs), instruction pointer (ip), and flags are pushed on the stack for storage, and a new cs and ip are loaded from a table that exists in the lowest 1024 bytes of memory. this table is referred to as the interrupt vector table and each entry is called an interrupt vector. once the new cs and ip are loaded from the interrupt vector table, the processor begins executing the code located at cs:ip. when the interrupt routine is completed, the cs, ip, and flags that were pushed on the stack when the interrupt occurred are now popped from the stack and execution resumes from the point where it was interrupted. ? using interrupts in your programs adding interrupts to your software is not as difficult as it may seem, and what they add in terms of perfor- mance is often worth the effort. note, however, that although it is not that hard to use interrupts, the smallest mistake will often lead to a system hang that requires a reboot. this can be both frustrating and time-consuming. but, after a few tries, youll get the bugs worked out and enjoy the benefits of properly executed interrupts. in addition to reading the following paragraphs, study the example programs included on your 3500 program disk for a better understanding of interrupt program development. ? writing an interrupt service routine (isr) the first step in adding interrupts to your software is to write the interrupt service routine (isr). this is the routine that will automatically be executed each time an interrupt request occurs on the specified irq. an isr is different than standard routines that you write. first, on entrance, the processor registers should be pushed onto the stack before you do anything else. second, just before exiting your isr, you must write an end-of-interrupt command to the 8259 controller(s). since 8259b generates a request on irq2 which is handled by 8259a, an eoi must be sent to both 8259a and 8259b for irq8-irq15. finally, when exiting the isr, in addition to popping all the registers you pushed on entrance, you must use the iret instruction and not a plain ret. the iret auto- matically pops the flags, cs, and ip that were pushed when the interrupt was called. if you find yourself intimidated by these requirements, take heart. most pascal and c compilers allow you to identify a procedure (function) as an interrupt type and will automatically add these instructions to your isr, with one important exception: most compilers do not automatically add the end-of-interrupt command to the proce- dure; you must do this yourself. other than this and the few exceptions discussed below, you can write your isr just like any other routine. it can call other functions and procedures in your program and it can access global data. if you are writing your first isr, we recommend that you stick to the basics; just something that will convince you that it works, such as incrementing a global variable. note: if you are writing an isr using assembly language, you are responsible for pushing and popping registers and using iret instead of ret. there are a few cautions you must consider when writing your isr. the most important is, do not use any dos functions or routines that call dos functions from within an isr . dos is not reentrant; that is, a dos function cannot call itself. in typical programming, this will not happen because of the way dos is written. but what about when using interrupts? then, you could have a situation such as this in your program. if dos function x is being executed when an interrupt occurs and the interrupt routine makes a call to dos function x, then function x is essentially being called while it is already active. such a reentrancy attempt spells disaster because dos functions are not written to support it. this is a complex concept and you do not need to understand it. just make sure that you do not call any dos functions from within your isr. the one wrinkle is that, unfortunately, it www.datasheet.co.kr datasheet pdf - http://www..net/
7-7 is not obvious which library routines included with your compiler use dos functions. a rule of thumb is that routines which write to the screen, or check the status of or read the keyboard, and any disk i/o routines use dos and should be avoided in your isr. the same problem of reentrancy exists for many floating point emulators as well, meaning you may have to avoid floating point (real) math in your isr. note that the problem of reentrancy exists, no matter what programming language you are using. even if you are writing your isr in assembly language, dos and many floating point emulators are not reentrant. of course, there are ways around this problem, such as those which involve checking to see if any dos functions are currently active when your isr is called, but such solutions are well beyond the scope of this discussion. the second major concern when writing your isr is to make it as short as possible in terms of execution time. spending long periods of time in your isr may mean that other important interrupts are being ignored. also, if you spend too long in your isr, it may be called again before you have completed handling the first run. this often leads to a hang that requires a reboot. your isr should have this structure: ? push any processor registers used in your isr. most c and pascal interrupt routines automatically do this for you. ? put the body of your routine here. ? issue the eoi command to the 8259 interrupt controller by writing 20h to port 20h and port a0h (if you are using irq8-irq15). ? pop all registers pushed on entrance. most c and pascal interrupt routines automatically do this for you. the following c and pascal examples show what the shell of your isr should be like: in c: void interrupt isr(void) { /* your code goes here. do not do not do not do not do not use any dos functions! */ outportb(0x20, 0x20); /* send eoi command to 8259a (for all irqs)*/ outportb(0x20, 0xa0); /* send eoi command to 8259b (if using irq8- 15) */ } in pascal: procedure isr; interrupt; begin { your code goes here. do not do not do not do not do not use any dos functions! } port[$20] := $20; { send eoi command to 8259a (for all irqs) } port[$a0] := $20; { send eoi command to 8259b (if using irq8- 15) } end; ? saving the startup interrupt mask register (imr) and interrupt vector the next step after writing the isr is to save the startup state of the interrupt mask register and the interrupt vector that you will be using. the imr for irq0-irq7 is located at i/o port 21h; the imr for irq8-irq15 is located at i/o port a1h. the interrupt vector you will be using is located in the interrupt vector table which is simply an array of 256 four-byte pointers and is located in the first 1024 bytes of memory (segment = 0, offset = 0). you can read this value directly, but it is a better practice to use dos function 35h (get interrupt vector). most c and pascal compilers provide a library routine for reading the value of a vector. the vectors for irq0-irq7 are vectors 8 through 15, where irq0 uses vector 8, irq1 uses vector 9, and so on. the vectors for irq8-irq15 are vectors 70h through 77h, where irq8 uses vector 70h, irq9 uses vector 71h, and so on. thus, if the ada3500 will be using irq15, you should save the value of interrupt vector 77h. www.datasheet.co.kr datasheet pdf - http://www..net/
7-8 before you install your isr, temporarily mask out the irq you will be using. this prevents the irq from requesting an interrupt while you are installing and initializing your isr. to mask the irq, read in the current imr at i/o port 21h for irq0-irq7, or at i/o port a1h for irq8-irq15 and set the bit that corresponds to your irq (remember, setting a bit disables interrupts on that irq while clearing a bit enables them). the imr on 8259a is arranged so that bit 0 is for irq0, bit 1 is for irq1, and so on. the imr on 8259b is arranged so that bit 0 is for irq8, bit 1 is for irq9, and so on. see the paragraph entitled interrupt mask register (imr) earlier in this chapter for help in determining your irqs bit. after setting the bit, write the new value to i/o port 21h (irq0- irq7) or i/o port a1h (irq8-irq15). with the startup imr saved and the interrupts on your irq temporarily disabled, you can assign the interrupt vector to point to your isr. again, you can overwrite the appropriate entry in the vector table with a direct memory write, but this is a bad practice. instead, use either dos function 25h (set interrupt vector) or, if your compiler provides it, the library routine for setting an interrupt vector. remember that vectors 8-15 are for irq0- irq7 and vectors 70h-77h are for irq8-irq15. if you need to program the source of your interrupts, do that next. for example, if you are using the program- mable interval timer to generate interrupts, you must program it to run in the proper mode and at the proper rate. finally, clear the bit in the imr for the irq you are using. this enables interrupts on the irq. ? restoring the startup imr and interrupt vector before exiting your program, you must restore the interrupt mask register and interrupt vectors to the state they were in before your program started. to restore the imr, write the value that was saved when your program started to i/o port 21h for irq0-irq7 or i/o port a1h for irq8-irq15. restore the interrupt vector that was saved at startup with either dos function 25h (set interrupt vector), or use the library routine supplied with your compiler. performing these two steps will guarantee that the interrupt status of your computer is the same after running your program as it was before your program started running. ? common interrupt mistakes ? remember that hardware interrupts are numbered 8 through 15 for irq0-irq7 and 70h through 77h for irq8-irq15. ? the most common mistake when writing an isr is forgetting to issue the eoi command to the appropriate 8259 interrupt controller before exiting the isr. ? be sure to clear the interrupt on the ada3500 board before issuing the eoi command. www.datasheet.co.kr datasheet pdf - http://www..net/
8-1 chapter 8 d/a conversions this chapter explains how to perform d/a conversions on the 3500. www.datasheet.co.kr datasheet pdf - http://www..net/
8-2 www.datasheet.co.kr datasheet pdf - http://www..net/
8-3 two independent 16-bit analog output channels are included on the ada3500. the analog outputs are generated by two 16-bit d/a converters that support dma transfer. dac1 data is written to ba + 12 and dac2 data is written to ba + 14. the configuration register, to set up the update select, is at ba + 10. the bit descrip- tion of this register is shown below. bits 0 and 1 C reserved. bits 2, 3 and 4 C these bits select the update source for dac 1. software uses the software command (read at ba + 10) to update the dac1 output; the a/d clock is used to synchronize the dac output to the a/d conversions; user tc out 2 uses the output of user tc, counter 2; dac1 clock uses the output of counter2 tc, counter 0; dac2 clock uses the output of counter2 tc, counter 1; external pacer clock uses the signal at p3 pin 41; external trigger uses the signal at p3 pin 39; and disable shuts off the update to the d/a converter. bits 5 and 6 C reserved. bits 7, 8 and 9 C these bits select the update source for dac 2. software uses the software command (read at ba + 10) to update the dac1 output; the a/d clock is used to synchronize the dac output to the a/d conversions; user tc out 2 uses the output of user tc, counter 2; dac1 clock uses the output of counter2 tc, counter 0; dac2 clock uses the output of counter2 tc, counter 1; external pacer clock uses the signal at p3 pin 41; external trigger uses the signal at p3 pin 39; and disable shuts off the update to the d/a converter. bits 10 and 11 C these bits enable the cycle mode for the d/a converters. by setting these bits to a 1, the d/ a will cotinuously repeat the data that is stored in the dac fifo.this is useful for waveform generation. bits 12 through 15 C these bits select the dma channel for transfers on the dac's. if you are using a/d and d/a dma, you must make sure that you select a different dma channel for the a/d, dac1 and dac2. when these bits are set to 0, the dma channels are disabled. a write programs the dac 16-bit output in the format shown below. output coding is two's complement format. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (msb) (lsb) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 00 00 dac2 dma channel select 00 = disabled 01 = drq5 10 = drq6 11 = drq7 dac1 dma channel select 00 = disabled 01 = drq5 10 = drq6 11 = drq7 dac2 update select 000 = software 001 = a/d clock 010 = user tc out 2 011 = dac1 clock 100 = dac2 clock 101 = external pacer clock 110 = external trigger 111 = disabled dac1 update select 000 = software 001 = a/d clock 010 = user tc out 2 011 = dac1 clock 100 = dac2 clock 101 = external pacer clock 110 = external trigger 111 = disabled dac2 cycle 0 = not cycle 1 = cycle dac1 cycle 0 = not cycle 1 = cycle www.datasheet.co.kr datasheet pdf - http://www..net/
8-4 the following tables list the key digital codes and corresponding output voltages for the d/a converters. d/a converter bit weights, bipolar, twos complement d/a bit weight ideal input voltage (millivolts) d/a bit weight ideal input voltage (millivolts) 1111 1111 1111 1111 -0.305176 0000 0000 1000 0000 +39.062500 1000 0000 0000 0000 -10000.000000 0000 0000 0100 0000 +19.531250 0100 0000 0000 0000 +5000.000000 0000 0000 0010 0000 +9.775625 0010 0000 0000 0000 +2500.000000 0000 0000 0001 0000 +4.882813 0001 0000 0000 0000 +1250.000000 0000 0000 0000 1000 +2.441406 0000 1000 0000 0000 +625.000000 0000 0000 0000 0100 +1.220703 0000 0100 0000 0000 +312.500000 0000 0000 0000 0010 +0.610352 0000 0010 0000 0000 +156.250000 0000 0000 0000 0001 +0.305176 0000 0001 0000 0000 +78.125000 0000 0000 0000 0000 0.000000 1024 sample buffer each dac channel has a 1024 sample buffer for storing data to be sent to the d/a converter. this means that you can fill the buffer with data and set up the d/a to output this data automatically. this is very useful for outputting high speed data or generating waveforms with precise timing requirements. by setting the cycle bit at ba + 10 , you can fill the buffer with one cycle of a wave, start the d/a update clock and the buffer will continue to repeat until the clock is stopped. combining this feature with the variety of update sources, you can build a flexible waveform generator. if you are trying to generate a non-repetitive waveform, you can combine the sample buffer capability with the dac sample counter. to utilize this feature of the ada3500 properly, you should load the buffer with data, program the dac sample counter for half the buffer size (512 samples) and use the sample counter to generate an interrupt. when an interrupt is received, you should reload the buffer with 512 new samples. by continuing this cycle, you can generate a non-repetitive waveform at high speeds. status of the fifo buffers can be monitored at ba + 2. any samples that are written to the fifo after it is full will be ignored. you can write up to 1024 samples to the buffer before it is full. each update pulse (either software or from one of the clocks) will remove a sample from the buffer and send it out the d/a. each read after the fifo buffer is empty will send 65535 (all "1's") out the d/a. at power-up or reset, the d/a outputs are set to 0 volts. before loading data into the sample buffer it is best to clear the buffer by writing and reading the proper bits at ba + 0. when you issue the "clear dac fifo" com- mand, all data in the buffer is erased. if you issue the "reset dac fifo" command, the data in the buffer is not erased, however the address pointer is set back to the beginning of the buffer: this is useful when you are generat- ing waveforms and stop the updating in the middle of a cycle. dac cycle bit the cycle bit is used to make the buffer data repeat. under normal operation, without the cycle bit set, data is written into the buffer and the update clock reads data out of the buffer. when the buffer is empty, the data will go to 65535 as explained above. if you set the cycle bit high, the data in the buffer will repeat. if you load a data set into the buffer, when the update clock reaches the end of the data it will automatically wrap around to the beginning and start over. this is useful for generating waveforms. www.datasheet.co.kr datasheet pdf - http://www..net/
8-5 dma transfer each dac buffer can be accessed through dma. this allows you to load d/a data into a memory buffer and have the cpu fill the fifo buffer automatically. this feature is useful if the amount of d/a data is greater than the 1024 samples that the fifo buffer will hold. a detailed discussion about dma transfers can be found in chapter 6. two important things to remember when using dma with the dac are to program the dma controller in the cpu for read operations, since you are reading data from memory and sending it out the d/a, and be sure to issue an "clear dac fifo" command at ba + 0 right before you unmask the dma channel bit. this will ensure proper dma operation. dac sample counter the dac sample counters, counter2 tc counter 2 for dac1 and counter1 tc counter 2 for dac2, are useful when using clocks to output data to the d/a. these counters will count update pulses sent to the d/a's and can be polled to read the current count or can be used to generate interrupts when the count reaches 0. these counters can be loaded to any starting value and count down. when the count reaches 0 it will automatically be reloaded with the original starting value. a read at ba + 8 provides a software trigger so that the dac sample counter can be loaded with the correct value. this software correction is used as an easy means to compensate for the operating structure of the 8254. two pulses of the counter are required to actually load the desired count and prepare the counter to count down correctly (this can be looked at as the initialization procedure for the dac sample counter). a pulse is sent to the dac sample counter (counter tc counter 2) each time you read this address. without this correction, the initial count sequence will be off by two pulses. once the counter is properly loaded and starts, any subsequent count- downs of this count will be accurate. you must select which dac sample counter to load by selecting the proper 8254 chip a register ba + 2. note that the dac sample counter must be programmed for mode 2 operation. www.datasheet.co.kr datasheet pdf - http://www..net/
8-6 www.datasheet.co.kr datasheet pdf - http://www..net/
9-1 chapter 9 timer/counters this chapter explains the three 8254 timer/counter circuits on the 3500. www.datasheet.co.kr datasheet pdf - http://www..net/
9-2 www.datasheet.co.kr datasheet pdf - http://www..net/
9-3 four 8254 programmable interval timers, clock tc, counter1 tc, counter2 tc and user tc, each provide three 16-bit, 8-mhz timers for timing and counting functions such as frequency measurement, event counting, and interrupts. two of the timers in the clock tc (u50) are cascaded and used for the on-board pacer clock, described in chapter 5. the third timer is the burst clock, also discussed in chapter 5. the 8254 at u51 is the counter1 tc. counter 0 is the a/d sample counter, counter 1 is the a/d delay counter, and counter 2 is the d/a 2 sample counter. the a/d sample counter and the a/d delay counter are discussed in chapter 5. the d/a 2 sample counter is discussed in chapter 8. the 8254 at u52 is the counter2 tc. counter 0 is the d/a 1 clock, counter 1 is the d/a 2 clock, and counter 2 is the d/a 1 sample counter. all of these timers are discussed in chapter 8. the 8254 at u53 is the user tc. all three counters on this chip are available for user functions. for details on the programming modes of the 8254, see the data sheet in appendix c. each timer/counter has two inputs, clk in and gate in, and one output, timer/counter out. they can be programmed as binary or bcd down counters by writing the appropriate data to the command word, as described in the i/o map discussion in chapter 4. jumper p10 is provided to give access to the counter outputs at p3 pins 43 and 44. the function of this jumper is described in chapter 1. the timers can be programmed to operate in one of six modes, depending on your application. the following paragraphs briefly describe each mode. mode 0, event counter (interrupt on terminal count). this mode is typically used for event counting. while the timer/counter counts down, the output is low, and when the count is complete, it goes high. the output stays high until a new mode 0 control word is written to the timer/counter. mode 1, hardware-retriggerable one-shot. the output is initially high and goes low on the clock pulse following a trigger to begin the one-shot pulse. the output remains low until the count reaches 0, and then goes high and remains high until the clock pulse after the next trigger. mode 2, rate generator. this mode functions like a divide-by-n counter and is typically used to generate a real-time clock interrupt. the output is initially high, and when the count decrements to 1, the output goes low for one clock pulse. the output then goes high again, the timer/counter reloads the initial count, and the process is repeated. this sequence continues indefinitely. mode 3, square wave mode. similar to mode 2 except for the duty cycle output, this mode is typically used for baud rate generation. the output is initially high, and when the count decrements to one-half its initial count, the output goes low for the remainder of the count. the timer/counter reloads and the output goes high again. this process repeats indefinitely. mode 4, software-triggered strobe. the output is initially high. when the initial count expires, the output goes low for one clock pulse and then goes high again. counting is triggered by writing the initial count. mode 5, hardware triggered strobe (retriggerable). the output is initially high. counting is triggered by the rising edge of the gate input. when the initial count has expired, the output goes low for one clock pulse and then goes high again. www.datasheet.co.kr datasheet pdf - http://www..net/
9-4 clock tc u50 counter 0 clk gate out counter 1 clk gate out counter 2 clk gate out 8mhz 16-bit pacer clock pacer clock gate control 32-bit pacer clock burst clock gate control burst clock counter1 tc u51 counter 0 clk gate out counter 1 clk gate out counter 2 clk gate out +5 v +5 v +5 v sample count clock sample count delay count clock delay count dac2 count clock dac2 count 3500 i/o connector p3 ext pclk pin 44 ext gate 1 ext clk user tc u53 counter 0 clk gate out counter 1 clk gate out counter 2 clk gate out 8mhz pin 45 pin 41 pin 42 pin 46 ext gate 2 +5 v p10 dig int 1 p9 counter2 tc u52 counter 0 clk gate out counter 1 clk gate out counter 2 clk gate out +5 v +5 v +5 v 8mhz dac1 clock 8mhz dac2 clock dac1 count clock dac1 count pin 43 dig int 2 fig. 9-1 user tc circuit diagram www.datasheet.co.kr datasheet pdf - http://www..net/
10-1 chapter 10 digital i/o this chapter explains the bit programmable and port program- mable digital i/o circuitry on the 3500. www.datasheet.co.kr datasheet pdf - http://www..net/
10-2 www.datasheet.co.kr datasheet pdf - http://www..net/
10-3 the 3500 has 32 buffered ttl/cmos digital i/o lines available for digital control applications. these lines are grouped in four 8-bit ports. the sixteen bits in port 0 and port 2 can be independently programmed as input or output. port 1 and port 3 can be programmed as 8-bit input or output ports. these lines are grouped in two digital i/o chips each with sixteen lines. chip 1 contains port 0 and port 1and chip 2 contains port 2 and port 3. both chips are addressed at ba + 24 through ba + 30. bit 9 at ba + 2 selects which digital i/o chip you are address- ing. port 0 and port 2, bit programmable digital i/o direction register: the sixteen port 0 and port 2 digital lines are individually set for input or output by writing to the direction register at ba + 28. the input lines are read and the output lines are written at ba + 24. advanced digital interrupts: mask and compare registers the port 0 and port 2 bits support two advanced digital interrupt modes. an interrupt can be generated when the data read at the port matches the value loaded into the compare register. this is called a match interrupt. or, an interrupt can be generated whenever any bit changes state. this is an event interrupt. for either interrupt, bits can be masked by setting the corresponding bit in the mask register high. in a digital interrupt mode, this masks out selected bits when monitoring the bit pattern for a match or event. in normal operation where the advanced digital interrupt mode is not activated, the mask register can be used to preserve a bits state, regardless of the digital data written to port 0 or port 2. when using event interrupts, you can determine which bit caused an event interrupt to occur by reading the contents latched into the compare register. port 1 and port 3, port programmable digital i/o the direction of the eight port 1 and port 3 digital lines is programmed at ba + 30, bit 2. these lines are configured as all inputs or all outputs, with their states read and written at ba + 26. resetting the digital circuitry when a digital chip clear (ba + 30, bits 1 and 0 = 00 followed by a write to ba + 28), clear board (ba + 0), or reset command is issued, all of the digital i/o lines are set up as inputs. strobing data into port 0 when not in an advanced digital interrupt mode, external data can be strobed into port 0 or port 2 by connecting a trigger pulse through the strb in pin at p3-41. this data can be read from the compare register at ba + 28. d7 d6 d5 d4 d3 d2 d1 d0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 for all bits: 0 = input 1 = output www.datasheet.co.kr datasheet pdf - http://www..net/
10-4 www.datasheet.co.kr datasheet pdf - http://www..net/
11-1 chapter 11 example programs this chapter discusses the example programs included with the AD3500 and ada3500. www.datasheet.co.kr datasheet pdf - http://www..net/
11-2 www.datasheet.co.kr datasheet pdf - http://www..net/
11-3 included with the 3500 is a set of example programs that demonstrate the use of many of the boards features. these examples are in written in c and basic. also included is an easy-to-use menu-driven diagnostics program, 3500diag, which is especially helpful when you are first checking out your board after installation and when calibrating the board (chapter 12). before using the software included with your board, make a backup copy of the disk. you may make as many backups as you need. c programs these programs are source code files so that you can easily develop your own custom software for your 3500. all of the programs use the files, drvr3500.c, dio5812.c and pcutils.c. these files contain all of the routines for setting up the board and acquiring data. drvr3500.c contains all the functions needed to control the a/d converter, the d/a converter and the timer/counters. these functions are used to set up the conversion type; set the trigger sources; program the pacer, burst and user clocks; read the a/d data and program the d/a outputs. dio5812.c contains all the functions needed to control the digital i/o chip. this chip is the same one used on the real time devices' dm5812 module providing two 8-bit ports. port 0 can have its lines set as input or output on a bit by bit basis. this allows maximum flexibility when connecting your signals. port 1 is set to be input or output as a group. in addition, port 0 supports rtds two advanced digital interrupt modes. an interrupt can be generated when the lines match a programmed value or when any bit changes its current state. a mask register lets you monitor selected lines for interrupt generation. pcutils.c contain functions to help program the cpu for interrupts and dma. quick basic programs these programs are source code files so that you can easily develop your own custom software for your 3500. all of the programs rely on the drvr3500.lib and the drvr3500.qlb library files. these library files contain all of functions needed to interface to the 3500. make sure the proper library is loaded when starting quick basic by typing qb/l drvr3500. these libraries were created using borland c 3.1 and were generated from the files drvr3500.c and dio5812.c. should you need to recompile the libraries, contact the factory for details on this procedure. www.datasheet.co.kr datasheet pdf - http://www..net/
11-4 www.datasheet.co.kr datasheet pdf - http://www..net/
12-1 chapter 12 calibration this chapter tells you how to calibrate the 3500 using the 3500diag calibration program included in the example software package and the trimpots on the board. these trimpots calibrate the a/d converter gain and offset, and the d/a converter gain and offset. www.datasheet.co.kr datasheet pdf - http://www..net/
12-2 www.datasheet.co.kr datasheet pdf - http://www..net/
12-3 this chapter tells you how to calibrate the a/d converter gain and offset and the d/a converter gain and offset. the offset and full-scale performance of the boards a/d and d/a converters are factory-calibrated. any time you suspect inaccurate readings, you can check the accuracy of your conversions using the procedures as needed below, and make adjustments as necessary. using the 3500diag diagnostics program is a convenient way to monitor conversions while you calibrate the board. the diagnostics program takes several samples and averages these readings in order to provide the most accurate data for calibration. calibration is done with the board installed in your system. you can access the trimpots at the top edge of the board. power up the system and let the board circuitry stabilize for 15 minutes before you start calibrating. required equipment the following equipment is required for calibration: ? precision voltage source: -10 to +10 volts ? digital voltmeter: 5-1/2 digits ? small screwdriver (for trimpot adjustment) while not required, the 3500diag diagnostics program (included with example software) is helpful when performing calibrations. figure 12-1 shows the board layout with the trimpots located along the top edge. www.datasheet.co.kr datasheet pdf - http://www..net/
12-4 fig. 12-1 board layout www.datasheet.co.kr datasheet pdf - http://www..net/
12-5 data values for calibrating bipolar 20 volt range (-10 to +10 volts) offset (tr4) input voltage = -0.1526mv converter gain (tr5) input voltage = -9.999847v a/d converted data 0000 0000 0000 0000 1111 1111 1111 1111 1000 0000 0000 0000 1000 0000 0000 0001 a/d converter bit weights, bipolar, twos complement a/d bit weight ideal input voltage (millivolts) 1111 1111 1111 1111 -0.305176 1000 0000 0000 0000 -10000.000000 0100 0000 0000 0000 +5000.000000 0010 0000 0000 0000 +2500.000000 0001 0000 0000 0000 +1250.000000 0000 1000 0000 0000 +625.000000 0000 0100 0000 0000 +312.500000 0000 0010 0000 0000 +156.250000 0000 0001 0000 0000 +78.125000 0000 0000 1000 0000 +39.062500 0000 0000 0100 0000 +19.531250 0000 0000 0010 0000 +9.775625 0000 0000 0001 0000 +4.882813 0000 0000 0000 1000 +2.441406 0000 0000 0000 0100 +1.220703 0000 0000 0000 0010 +0.610352 0000 0000 0000 0001 +0.305176 0000 0000 0000 0000 0.000000 a/d calibration the following paragraphs describe the procedure for calibrating the a/d converter over the -10 to +10 volt input range. the table below shows the ideal voltage for each bit weight for this bipolar, twos complement range. two adjustments are made to calibrate the a/d converter. one is the offset adjustment, and the other is the full scale, or gain, adjustment. trimpot tr4 is used to make the offset adjustment, and trimpot tr5 is used for gain adjustment. use analog input channel 1 and set it for a gain of 1 while calibrating the module. connect your precision voltage source to channel 1. set the voltage source to -0.1526 millivolts, start a conversion, and read the resulting data. adjust trimpot tr4 until it flickers between the values listed in the table below. next, set the voltage to -9.999847 volts, and repeat the procedure, this time adjusting tr5 until the output matches the data in the table below. www.datasheet.co.kr datasheet pdf - http://www..net/
12-6 gain adjustment should you find it necessary to check any of the programmable gain settings, the following table will show the proper trimpot to adjust. d/a calibration the following paragraphs describe the procedure for calibrating the d/a converter over the -10 to +10 volt output range. the table below shows the ideal voltage for each bit weight for this bipolar, twos complement range. trimpots for calibrating gains gain trimpot x2 tr7 x4 tr8 x8 tr9 x16 tr10 x32 tr11 x64 tr12 x128 tr13 d/a converter bit weights, bipolar, twos complement d/a bit weight ideal input voltage (millivolts) d/a bit weight ideal input voltage (millivolts) 1111 1111 1111 1111 -0.305176 0000 0000 1000 0000 +39.062500 1000 0000 0000 0000 -10000.000000 0000 0000 0100 0000 +19.531250 0100 0000 0000 0000 +5000.000000 0000 0000 0010 0000 +9.775625 0010 0000 0000 0000 +2500.000000 0000 0000 0001 0000 +4.882813 0001 0000 0000 0000 +1250.000000 0000 0000 0000 1000 +2.441406 0000 1000 0000 0000 +625.000000 0000 0000 0000 0100 +1.220703 0000 0100 0000 0000 +312.500000 0000 0000 0000 0010 +0.610352 0000 0010 0000 0000 +156.250000 0000 0000 0000 0001 +0.305176 0000 0001 0000 0000 +78.125000 0000 0000 0000 0000 0.000000 two adjustments are made to calibrate each d/a converter. one is the offset adjustment, and the other is the full scale, or gain, adjustment. trimpot tr14 (dac 1) or tr16 (dac 2) is used to make the offset adjustment, and trimpot tr15 (dac 1) or tr17 (dac 2) is used for gain adjustment. connect a precision voltmeter to measure the dac output. output a value of 1000 0000 0000 0000 and read the corresponding output voltage. the voltage should be -10.00000 volts as shown in the table below. adjust tr14 or tr16 as needed to obtain the correct output voltage. next, output a value of 0111 1111 1111 1111 and read the corresponding output voltage. the voltage should be the positive full-scale value of +9.999694 volts, as shown in the table below. adjust tr15 or tr17 as needed to obtain the correct output voltage. www.datasheet.co.kr datasheet pdf - http://www..net/
12-7 data values for calibrating bipolar 20 volt range (-10 to +10 volts) offset (tr14 or tr16) output = 1000 0000 0000 0000 converter gain (tr15 or tr17) output = 0111 1111 1111 1111 d/a output voltage -10.000000 volts +9.999694 volts www.datasheet.co.kr datasheet pdf - http://www..net/
12-8 www.datasheet.co.kr datasheet pdf - http://www..net/
a-1 appendix a AD3500/ada3500 specifications www.datasheet.co.kr datasheet pdf - http://www..net/
a-2 www.datasheet.co.kr datasheet pdf - http://www..net/
a-3 AD3500/ada3500 characteristics typical @ 25 c interface ibm pc/at compatible switch-selectable base address, i/o mapped software-selectable interrupts software-selectable dma channel analog input up to 8 diff, 8 se with dedicated ground, 16 se inputs, software selectable input impedance, each channel ............................................................. >10 megohms gains, software-selectable .................................................. 1, 2, 4, 8, 16, 32, 64, 128 gain error .................................................................................. 0.05%, typ; 0.1%, max input range ..................................................................................................... 10 volts overvoltage protection ..................................................................................... 12 vdc common mode input voltage ................................................................. 10 volts, max settling time (gain = 1) ............................................................................. 10 sec, max a/d converter type .................................................................................... successive approximation resolution ............................................................................................ 16 bits (305 uv) linearity ................................................................................................... 1.5 lsb, typ conversion speed ...................................................................................... 10 sec, typ throughput ....................................................................................................... 100 khz noise .......................................................................................................... 2 lsb, typ channel-gain table size ......................................................................................................... 1024 x 24 bits pacer clock & sample counter range (using on-board 8 mhz clock) .......................................... 9 minutes to 10 sec sample counter maximum count (1 cycle) ........................................................ 65,536 digital i/o number of lines ................................... 16 bit programmable & 16 port programmable isource ............................................................................................................... -12 ma isink ..................................................................................................................... 24 ma a/d sample buffer fifo size ................................................................................................ 1024 x 16 bits d/a converter (ada3500 only) analog outputs ............................................................................................. 2 channels resolution ........................................................................................................... 16 bits output range ................................................................................................. 10 volts relative accuracy ..................................................................................... 4 lsb, max full-scale accuracy .................................................................................. 4 lsb, max non-linearity ............................................................................................. 4 lsb, max settling time ............................................................................................... 10 sec, typ output current ................................................................................................ 5 ma, typ d/a sample buffer fifo size (each channel) ....................................................................... 1024 x 16 bits www.datasheet.co.kr datasheet pdf - http://www..net/
a-4 timer/counters .............................................................................. cmos 82c54 twelve 16-bit down counters (3 per ic) binary or bcd counting programmable operating modes (6) ............................................. interrupt on terminal count; programmable one-shot; rate generator; square wave rate generator; software-triggered strobe; hardware-triggered strobe counter input source ................................................... external clock (8 mhz, max) or on-board 8-mhz clock counter outputs ........................................ available externally; used as pc interrupts counter gate source .................................................. external gate or always enabled miscellaneous inputs/outputs (pc bus-sourced) +5 volts 12 volts ground current requirements +5 volts .............................................................................................................. 750 ma connectors: p3: 50-pin d-type connector p4: 50-pin box connector environmental operating temperature ................................................................................. 0 to +70c storage temperature ................................................................................. -40 to +85c humidity ............................................................................... 0 to 90% non-condensing size 3.875"h x 13.20"l (99mm x 335mm) www.datasheet.co.kr datasheet pdf - http://www..net/
b-1 appendix b p3 & p4 connector pin assignments www.datasheet.co.kr datasheet pdf - http://www..net/
b-2 www.datasheet.co.kr datasheet pdf - http://www..net/
b-3 p3 connector: p3 mating connector part numbers manufacturer part number amphenol 850-57f-30500-20 39 40 37 38 35 36 33 34 31 32 29 30 27 28 25 26 23 24 21 22 19 20 17 18 15 16 13 14 11 12 9 10 7 8 5 6 3 4 1 2 49 50 47 48 45 46 43 44 41 42 ain1- ain9 / agnd ain2- ain10 / agnd ain3- ain11 / agnd ain4- ain12 / agnd ain5- ain13 / agnd ain6- ain14 / agnd ain7- ain15 / agnd ain8- ain16 / agnd analog gnd analog gnd analog gnd p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 digital gnd ext gate 1 clk out1 / clk out2 ext gate 2 +5 volts digital gnd ain1+ ain2+ ain3+ ain4+ ain4+ ain6+ ain7+ ain8+ ain1 ain2 ain3 ain4 ain5 ain6 ain7 ain8 aout 1 aout 2 analog gnd p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 trigger in ext pacer clk clk out0 / dig irq ext clk +12 volts -12 volts diff. s.e. diff. s.e. 39 40 37 38 35 36 33 34 31 32 29 30 27 28 25 26 23 24 21 22 19 20 17 18 15 16 13 14 11 12 9 10 7 8 5 6 3 4 1 2 49 50 47 48 45 46 43 44 41 42 digital gnd digital gnd digital gnd digital gnd digital gnd digital gnd digital gnd digital gnd n.c. n.c. digital gnd p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 digital gnd n.c. n.c. n.c. +5 volts digital gnd n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. digital gnd p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 ext int n.c. n.c. n.c. +12 volts -12 volts p4 connector: p4 mating connector part numbers manufacturer part number amp 1-746094-0 3m 3425-7650 www.datasheet.co.kr datasheet pdf - http://www..net/
b-4 www.datasheet.co.kr datasheet pdf - http://www..net/
c-1 appendix c component data sheets www.datasheet.co.kr datasheet pdf - http://www..net/
c-2 www.datasheet.co.kr datasheet pdf - http://www..net/
c-3 intel 82c54 programmable interval timer data sheet reprint www.datasheet.co.kr datasheet pdf - http://www..net/
c-4 www.datasheet.co.kr datasheet pdf - http://www..net/
d-1 appendix d warranty www.datasheet.co.kr datasheet pdf - http://www..net/
d-2 www.datasheet.co.kr datasheet pdf - http://www..net/
d-3 limited warranty real time devices, inc. warrants the hardware and software products it manufactures and produces to be free from defects in materials and workmanship for one year following the date of shipment from real time de- vices. this warranty is limited to the original purchaser of product and is not transferable. during the one year warranty period, real time devices will repair or replace, at its option, any defective products or parts at no additional charge, provided that the product is returned, shipping prepaid, to real time devices. all replaced parts and products become the property of real time devices. before returning any product for repair, customers are required to contact the factory for an rma number. this limited warranty does not extend to any products which have been dam- aged as a result of accident, misuse, abuse (such as: use of incorrect input voltages, improper or insufficient ventilation, failure to follow the operating instructions that are provided by real time devices, acts of god or other contingencies beyond the control of real time devices), or as a result of service or modification by anyone other than real time devices. except as ex- pressly set forth above, no other warranties are expressed or implied, including, but not limited to, any implied warranties of merchantability and fitness for a particular purpose, and real time devices expressly disclaims all warranties not stated herein. all implied warranties, including implied warranties for mechantability and fitness for a particular purpose, are limited to the duration of this warranty. in the event the product is not free from defects as warranted above, the purchasers sole remedy shall be repair or replacement as provided above. under no circumstances will real time devices be liable to the purchaser or any user for any damages, including any incidental or consequential dam- ages, expenses, lost profits, lost savings, or other damages arising out of the use or inability to use the product. some states do not allow the exclusion or limitation of incidental or conse- quential damages for consumer products, and some states do not allow limita- tions on how long an implied warranty lasts, so the above limitations or exclu- sions may not apply to you. this warranty gives you specific legal rights, and you may also have other rights which vary from state to state. www.datasheet.co.kr datasheet pdf - http://www..net/
ada3500 user settings base i/o address: (hex) (decimal) irq channel: dma channel: www.datasheet.co.kr datasheet pdf - http://www..net/

▲Up To Search▲

Price & Availability of AD3500

	To Download AD3500 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .